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參數(shù)資料
| 型號： | T7256A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 30/116頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | T7256A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
26
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Registers
(continued)
Table 8. Data Flow Control—D Channels and TDM Bus (Address 04h)
Bits 2—7 are enabled only if TDMEN = 0 (register GR2, bit 5). The TDMCLK and FS outputs are activated if any
one of bits 2—7 is enabled. The TDMDO output is activated during time slots enabled by programming bits 2—7.
Reg
DFR1
Default State on RESET
R/W
R/W
Bit 7
TDMDU
1
Bit 6
TDMB2U
1
Bit 5
TDMB1U
1
Bit 4
TDMDS
1
Bit 3
TDMB2S TDMB1S
1
Bit 2
Bit 1
SXD
1
Bit 0
UXD
1
1
Register Bit
DFR1
Symbol
UXD
Name/Description
0
U-Interface Transmit Path Source for D Channel.
Refer to point #1 in Figure 16.
0—TDM bus.
1—S/T-interface receive (default).
S/T-Interface Transmit Path Source for D Channel.
Refer to point #2 in Figure 16.
0—TDM bus.
1—U-interface receive (default).
TDMB1S
TDM Bus Transmit Control for B1 Channel from S/T-Interface.
Refer to point #3 in
Figure 16. Controls transmit time slot allocated on TDM bus for B1 channel derived
from S/T-interface receiver.
0—Time slot enabled.
1—Time slot disabled (high impedance) (default).
TDMB2S
TDM Bus Transmit Control for B2 Channel from S/T-Interface.
Refer to point #3 in
Figure 16. Controls transmit time slot allocated on TDM bus for B2 channel derived
from S/T-interface receiver.
0—Time slot enabled.
1—Time slot disabled (high impedance) (default).
TDMDS
TDM Bus Transmit Control for D Channel from S/T-Interface.
Refer to point #3 in
Figure 16. Controls transmit time slot allocated on TDM bus for D channel derived from
S/T-interface receiver.
0—Time slot enabled.
1—Time slot disabled (high impedance) (default).
TDMB1U
TDM Bus Transmit Control for B1 Channel from U-Interface.
Refer to point #3 in
Figure 16. Controls transmit time slot allocated on TDM bus for B1 channel derived
from U-interface receiver.
0—Time slot enabled.
1—Time slot disabled (high impedance) (default).
TDMB2U
TDM Bus Transmit Control for B2 Channel from U-Interface.
Refer to point #3 in
Figure 16. Controls transmit time slot allocated on TDM bus for B2 channel derived
from U-interface receiver.
0—Time slot enabled.
1—Time slot disabled (high impedance) (default).
TDMDU
TDM Bus Transmit Control for D Channel from U-Interface.
Refer to point #3 in
Figure 16. Controls transmit time slot allocated on TDM bus for D channel derived from
U-interface receiver.
0—Time slot enabled.
1—Time slot disabled (high impedance) (default).
DFR1
1
SXD
DFR1
2
DFR1
3
DFR1
4
DFR1
5
DFR1
6
DFR1
7
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