- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383876 > T7256A Compliance with the New ETSI PSD Requirement PDF資料下載
參數(shù)資料
| 型號(hào)： | T7256A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁(yè)數(shù)： | 15/116頁(yè) |
| 文件大?。?/td> | 1056K |
| 代理商： | T7256A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
11
Functional Overview
The T7256 device provides four major interfaces for
information transfer: the U-interface, the S/T-interface,
the microprocessor interface, and the time-division
multiplexed (TDM) bus interface (see Figure 1). Use of
the microprocessor and TDM bus interface is optional.
If the microprocessor and TDM interfaces aren’t
required, the T7234 SCNT1 Euro-LITE may be a more
cost-effective solution (see the T7234 SCNT1 Euro-
LITE Single-Chip NT1 Data Sheet). Similarly, if an S/T-
interface is not required, the T7237 may be a more
cost-effective solution (see the T7237 ISDN U-Interface
Transceiver Data Sheet). These devices are pin-com-
patible with the T7256, but have a reduced feature set
for cost-sensitive applications that don’t require the full
feature set of the T7256.
Routing of data between the S/T, U, and TDM inter-
faces is controlled by the data flow matrix that uses
register settings accessible via the microprocessor
port. The data flow matrix circuitry routes 2B+D infor-
mation between the appropriate interfaces, under
direction of the microprocessor register settings. Rout-
ing between the T7256 interfaces allows configurations
to support both NT1 and TA applications.
The architecture of the T7256 allows for a flexible com-
bination of automatically and manually controlled func-
tions. A control flow state machine, eoc state machine,
and multiframing controller can be independently
enabled or disabled. When enabled, these circuit
blocks automatically perform their functions while
ignoring the associated control bits in the microproces-
sor registers. When disabled, the control bits are made
available to the microprocessor for manipulation. At all
times, the status bits are available to the microproces-
sor and the 2B+D data can be routed via the data flow
matrix.
The microprocessor interface is a serial communica-
tions port consisting of input data (SDI), output data
(SDO), input clock (SCK), and an output interrupt pin
(INT). The microprocessor interface supports synchro-
nous communication between the T7256 and an inex-
pensive microprocessor with a serial port. The interrupt
is maskable via the onboard microprocessor interrupt
mask registers. The internal register set controls vari-
ous functions including information routing between
interfaces, auto-eoc processing, maintenance testing,
S/T-interface timing recovery mode, S- and Q-channel
processing, microprocessor interrupt masks, activation
of the TDM bus, and frame strobe timing.
The TDM interface consists of a TDM bus data clock
(TDMCLK), input data (TDMDI), output data (TDMDO),
and frame strobe (FS). The 2B+D data is transmitted
and received in fixed time slots on the TDM bus; how-
ever, the frame strobe output lead is programmable to
support a wide variety of devices (codecs, HDLC pro-
cessors, asynchronous interfaces) for direct connection
on the TDM bus. The TDM bus exists as a selectable
option via the microprocessor interface. When the TDM
bus is activated, pins 4, 7, 8, and 9 are reconfigured to
form the bus interface.
The eoc state machine, when enabled, automatically
performs the eoc channel functions as described in the
ANSI requirements. When disabled, control of the eoc
channel is passed to the microprocessor via the appro-
priate microprocessor register bits.
The ANSI maintenance controller can operate in
fully automatic or in fully manual mode. In automatic
mode, the device decodes and responds to mainte-
nance states according to the ANSI requirements. In
manual mode, the device is controlled by an external
maintenance decoder that drives the RESET and
ILOSS pins to implement the required maintenance
states.
The multiframing controller, when enabled, allows the S
and Q channels on the S/T-interface to be manipulated
by the microprocessor. When disabled, the S- and Q-
channel bits are automatically loaded with their default
values for applications not supporting multiframing.
The control flow state machine performs the functions
of reserved bit insertion, automatic implementation of
the ANSI maintenance state machine, and automatic
prioritization of multiple requests, such as reset, activa-
tion, maintenance, etc. Some bits that are normally
controlled by the control flow state machine can be
forced to their active state by writing the appropriate
register (i.e., register GR1). When the control flow state
machine is disabled (via the AUTOCTL bit in register
GR0), the only change in the operation is that reserved
bit control and ANSI maintenance control are passed
directly to the microprocessor via register CFR0.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T7288 | CEPT/E1 Line Interface(CEPT/E1 線接口) |
| T7290A | DS1/T1/CEPT/E1 Line Interface(DS1/T1/CEPT/E1 線接口) |
| T7295-1 | E3 Integrated Line Receiver(E3 集成線接收器) |
| T7295-6 | DS3/SONET STS-1 Integrated Line Receiver(DS3/SONET STS-1 集成線接收器) |
| T7296 | Integrated Line Transmitter(集成PCM線傳送器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T7257 | 制造商:TE Connectivity 功能描述: |
| T-726 | 制造商:RHOMBUS-IND 制造商全稱:Rhombus Industries Inc. 功能描述:ADSL Line Interface Transformers |
| T7263 | 制造商:TE Connectivity 功能描述: |
| T7263A | 制造商:Toshiba America Electronic Components 功能描述:T7263A |
| T7264 | 制造商:TE Connectivity 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。