參數(shù)資料
型號： S-7600A
廠商： Seiko Instruments Inc.
英文描述： Hardware Specification (TCP/IP Network Stack LSI)
中文描述： 硬件規(guī)格（TCP / IP網(wǎng)絡(luò)堆棧大規(guī)模集成電路）
文件頁數(shù)： 6/60頁
文件大小： 371K
代理商： S-7600A
TCP/IP Network Stack LSI
S-7600A
Hardware Specification
Revision 1.3
iv
Seiko Instruments Inc.
LIST OF TABLES
T
ABLE
3-1 P
IN
A
SSIGNMENT
.................................................................................................................. 3-1
T
ABLE
3-2 P
IN
D
ESCRIPTION
.................................................................................................................. 3-3
T
ABLE
4-1 A
BSOLUTE
M
AXIMUM
R
ATINGS
.............................................................................................. 4-1
T
ABLE
4-2 R
ECOMMENDED
O
PERATING
C
ONDITIONS
.............................................................................. 4-1
T
ABLE
4-3 DC
C
HARACTERISTICS
.......................................................................................................... 4-2
T
ABLE
4-4 P
OWER
C
URRENT
C
ONSUMPTION
.......................................................................................... 4-2
T
ABLE
5-1 I
NTERFACE
S
ELECTION
.......................................................................................................... 5-1
T
ABLE
5-2 C
ONNECTION
R
ELATIONSHIP BETWEEN
MPU
AND
P
INS
.......................................................... 5-1
T
ABLE
5-3 68
K
F
AMILY
MPU W
RITE
C
YCLE
T
IMING
................................................................................ 5-2
T
ABLE
5-4 68
K
F
AMILY
MPU R
EAD
C
YCLE
T
IMING
................................................................................. 5-3
T
ABLE
5-5
X
80 F
AMILY
MPU W
RITE
C
YCLE
T
IMING
................................................................................ 5-4
T
ABLE
5-6
X
80 F
AMILY
MPU R
EAD
C
YCLE
T
IMING
................................................................................. 5-5
T
ABLE
5-7 S
ERIAL
I
NTERFACE
W
RITE
C
YCLE
T
IMING
.............................................................................. 5-6
T
ABLE
5-8 S
ERIAL
I
NTERFACE
R
EAD
C
YCLE
T
IMING
................................................................................ 5-7
T
ABLE
5-9 I
NTERRUPT
S
ELECTION
T
ABLE
............................................................................................... 5-8
T
ABLE
6-1 S-7600A M
EMORY
M
AP
(B
ANK
0)......................................................................................... 6-2
T
ABLE
6-2 S-7600A M
EMORY
M
AP
(B
ANK
1)......................................................................................... 6-2
T
ABLE
7-1
I
API R
EGISTER
M
AP
............................................................................................................. 7-2
T
ABLE
7-2
I
API R
EGISTER
M
AP
(C
ONTINUED
) ........................................................................................ 7-3
T
ABLE
7-3 R
EVISION
R
EGISTER
B
IT
D
EFINITIONS
.................................................................................... 7-4
T
ABLE
7-4 R
EVISION
R
EGISTER
D
ESCRIPTION
........................................................................................ 7-4
T
ABLE
7-5 G
ENERAL
C
ONTROL
R
EGISTER
B
IT
D
EFINITIONS
.................................................................... 7-4
T
ABLE
7-6 G
ENERAL
C
ONTROL
R
EGISTER
D
ESCRIPTION
......................................................................... 7-4
T
ABLE
7-7 G
ENERIC
S
OCKET
L
OCATION
R
EGISTER
B
IT
D
EFINITIONS
....................................................... 7-5
T
ABLE
7-8 G
ENERIC
S
OCKET
L
OCATION
R
EGISTER
D
ESCRIPTION
........................................................... 7-5
T
ABLE
7-9 M
ASTER
I
NTERRUPT
R
EGISTER
B
IT
D
EFINITIONS
.................................................................... 7-5
T
ABLE
7-10 M
ASTER
I
NTERRUPT
R
EGISTER
D
ESCRIPTIONS
(C
ONTINUED
)............................................... 7-6
T
ABLE
7-11 C
ONF
S
TATUS
R
EGISTER
B
IT
D
EFINITIONS
........................................................................... 7-6
T
ABLE
7-12 C
ONF
S
TATUS
R
EGISTER
D
ESCRIPTION
............................................................................... 7-7
T
ABLE
7-13 S
ERIAL
P
ORT
I
NTERRUPT
R
EGISTER
B
IT
D
EFINITIONS
.......................................................... 7-8
T
ABLE
7-14 S
ERIAL
P
ORT
I
NTERRUPT
R
EGISTER
D
ESCRIPTION
............................................................... 7-8
T
ABLE
7-15 S
ERIAL
P
ORT
I
NTERRUPT
M
ASK
R
EGISTER
B
IT
D
EFINITIONS
................................................. 7-8
T
ABLE
7-16 S
ERIAL
P
ORT
I
NTERRUPT
M
ASK
R
EGISTER
D
ESCRIPTION
..................................................... 7-8
T
ABLE
7-17 O
UR
IP A
DDRESS
R
EGISTER
B
IT
D
EFINITIONS
(0
X
10) .......................................................... 7-9
T
ABLE
7-18 O
UR
IP A
DDRESS
R
EGISTER
B
IT
D
EFINITIONS
(0
X
11) .......................................................... 7-9
T
ABLE
7-19 O
UR
IP A
DDRESS
R
EGISTER
B
IT
D
EFINITIONS
(0
X
12) ........................................................ 7-10
T
ABLE
7-20 O
UR
IP A
DDRESS
R
EGISTER
B
IT
D
EFINITIONS
(0
X
13) ........................................................ 7-10
T
ABLE
7-21 I
NDEX
R
EGISTER
B
IT
D
EFINITION
....................................................................................... 7-10
T
ABLE
7-22 I
NDEX
R
EGISTER
D
ESCRIPTION
.......................................................................................... 7-10
T
ABLE
7-23 S
OCKET
C
ONFIG
S
TATUS
L
OW
R
EGISTER
B
IT
D
EFINITIONS
................................................ 7-11
T
ABLE
7-24 S
OCKET
C
ONFIG
S
TATUS
L
OW
R
EGISTER
D
ESCRIPTION
..................................................... 7-12
T
ABLE
7-25 S
OCKET
S
TATUS
M
ID
R
EGISTER
B
IT
D
EFINITIONS
.............................................................. 7-13
T
ABLE
7-26 S
OCKET
S
TATUS
M
ID
R
EGISTER
D
ESCRIPTION
................................................................... 7-13
T
ABLE
7-27 S
OCKET
A
CTIVATE
R
EGISTER
B
IT
D
EFINITIONS
.................................................................. 7-14
T
ABLE
7-28 S
OCKET
A
CTIVATE
R
EGISTER
D
ESCRIPTION
....................................................................... 7-14
T
ABLE
7-29 S
OCKET
I
NTERRUPT
R
EGISTER
B
IT
D
EFINITIONS
................................................................ 7-14
T
ABLE
7-30 S
OCKET
I
NTERRUPT
R
EGISTER
D
ESCRIPTION
.................................................................... 7-15
T
ABLE
7-31 S
OCKET
D
ATA
A
VAIL
R
EGISTER
B
IT
D
EFINITIONS
............................................................... 7-15
T
ABLE
7-32 S
OCKET
D
ATA
A
VAIL
R
EGISTER
D
ESCRIPTION
................................................................... 7-15
T
ABLE
7-33 S
OCKET
I
NTERRUPT
M
ASK
L
OW
R
EGISTER
B
IT
D
EFINITIONS
.............................................. 7-16
T
ABLE
7-34 S
OCKET
I
NTERRUPT
M
ASK
L
OW
R
EGISTER
D
ESCRIPTION
................................................... 7-16
T
ABLE
7-35 S
OCKET
I
NTERRUPT
M
ASK
H
IGH
R
EGISTER
B
IT
D
EFINITIONS
.............................................. 7-16
T
ABLE
7-36 S
OCKET
I
NTERRUPT
M
ASK
H
IGH
R
EGISTER
D
ESCRIPTION
.................................................. 7-16
T
ABLE
7-37 S
OCKET
I
NTERRUPT
L
OW
R
EGISTER
B
IT
D
EFINITIONS
........................................................ 7-17
T
ABLE
7-38 S
OCKET
I
NTERRUPT
L
OW
R
EGISTER
D
ESCRIPTION
............................................................. 7-17
T
ABLE
7-39 S
OCKET
I
NTERRUPT
H
IGH
R
EGISTER
B
IT
D
EFINITIONS
....................................................... 7-17
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