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| 型號(hào)： | S-7600A |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | Hardware Specification (TCP/IP Network Stack LSI) |
| 中文描述： | 硬件規(guī)格（TCP / IP網(wǎng)絡(luò)堆棧大規(guī)模集成電路） |
| 文件頁數(shù)： | 42/60頁 |
| 文件大小： | 371K |
| 代理商： | S-7600A |
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TCP/IP Network Stack LSI
S-7600A
Hardware Specification
Revision 1.3
7-15
Seiko Instruments Inc.
Table 7-30
Socket Interrupt Register Description
Bit
Bit Name
Access
Description
1
1
R
This bit is used to indicate that socket 1 has an
interrupt pending.
0 = General socket 1 interrupt inactive
1 = General socket 1 interrupt active
0
0
R
This bit is used to indicate that socket 0 has an
interrupt pending.
0 = General socket 0 interrupt inactive
1 = General socket 0 interrupt active
7.3.18. Socket Data Available Register (0x28)
(Read-Only, Default 0x00)
This read-only register indicates which socket has data pending in the input buffer. A “1” in a bit position
indicates that the socket has data available. The bit remains set as long as there is data available.
Table 7-31
Socket Data Avail Register Bit Definitions
Bit
7
6
5
4
3
2
1
0
Def.
DAV1
DAV0
Default
0
0
0
0
0
0
0
0
Table 7-32
Socket Data Avail Register Description
Bit
Bit Name
Access
Description
1
DAV1
R
This bit is used to indicate that socket 1 has data
available.
0 = General socket 1 has no data available
1 = General socket 1 has data available
0
DAV0
R
This bit is used to indicate that socket 0 has data
available.
0 = General socket 0 has no data available
1 = General socket 0 has data available
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