參數(shù)資料
型號(hào)： S-7600A
廠商： Seiko Instruments Inc.
英文描述： Hardware Specification (TCP/IP Network Stack LSI)
中文描述： 硬件規(guī)格（TCP / IP網(wǎng)絡(luò)堆棧大規(guī)模集成電路）
文件頁(yè)數(shù)： 43/60頁(yè)
文件大?。?/td> 371K
代理商： S-7600A
TCP/IP Network Stack LSI
S-7600A
Hardware Specification
Revision 1.3
Seiko Instruments Inc.
7-16
7.3.19. Socket Interrupt Mask Low Register (0x2A)
(Read/Write, Default 0x00)
This register reports certain interrupt conditions. Setting a bit enables the corresponding interrupt.
Table 7-33
Socket Interrupt Mask Low Register Bit Definitions
Bit
Def.
7
6
5
4
3
2
1
0
TO_En
Buff_
Emp_En
Buff_Full_En
Data_Avail_En
Default
0
0
0
0
0
0
0
0
NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.
Table 7-34
Socket Interrupt Mask Low Register Description
Bit
Bit Name
Access
Description
7
TO_En
R/W
Writing a “1” enables the Timeout interrupt.
6
Buff_Empty_En
R/W
Writing a “1” enables the Buffer Empty interrupt.
5
Buff_Full_En
R/W
Writing a “1” enables the Buffer Full interrupt.
4
Data_Avail_En
R/W
Writing a “1” enables the Data Available interrupt.
7.3.20. Socket Interrupt Mask High Register (0x2B)
(Read/Write, Default 0x00)
This register enables certain types of interrupt conditions. Setting bits enables their corresponding
interrupts.
Table 7-35
Socket Interrupt Mask High Register Bit Definitions
Bit
Def.
7
6
5
4
3
2
1
0
URG_En
RST_En
Term_En
ConU_En
Default
0
0
0
0
0
0
0
0
NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.
Table 7-36
Socket Interrupt Mask High Register Description
Bit
Bit Name
Access
Description
7
URG_En
R/W
Writing a “1” to enable the Urgent Data interrupt.
6
RST_En
R/W
Writing a “1” to enable the Connection Reset interrupt.
5
Term_En
R/W
Writing a “1” to enable the Socket Termination interrupt.
4
ConU_En
R/W
Writing a “1” to enable the Connection Up interrupt.
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