參數(shù)資料
型號(hào)： S-7600A
廠商： Seiko Instruments Inc.
英文描述： Hardware Specification (TCP/IP Network Stack LSI)
中文描述： 硬件規(guī)格（TCP / IP網(wǎng)絡(luò)堆棧大規(guī)模集成電路）
文件頁(yè)數(shù)： 56/60頁(yè)
文件大小： 371K
代理商： S-7600A
TCP/IP Network Stack LSI
S-7600A
Hardware Specification
Revision 1.3
9-1
Seiko Instruments Inc.
9. Reset Functions
9.1. Overview
The S-7600A has two reset functions which are hardware reset and software reset.
9.1.1. Hardware Reset Function
The S-7600A operates to be synchronous to the
CLK
signal(clock input). When the
RESETX
pin set to
low level in two clock period minimum, the S-7600A accept hardware reset input and starts initializing
internal circuit at positive edge timing of forth clock. After the
RESETX
pin return to high level, the S-
7600A maintains initialized state and turns normal state at positive edge timing of forth clock.
See the Figure 9-1.
Figure 9-1
Hardware Reset Timing
9.1.2. Software Reset Function
The S-7600A is able to initialize the internal circuit by the
General Control
Register(0x01). Show the reset
timing in case of x80 Family MPU mode. See the Figure 9-2.
Figure 9-2
Software Reset Timing
initialized
2nd
1st
3rd
4th
4th
3rd
2nd
1st
CLK
RESETX
Min. 2 clock
normal
normal state
normal state
CS
CLK
BUSYX
WRITEX
RS
SD7 to 0
Address
Data h01
initialized state
x80 Family MPU mode
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