參數(shù)資料
型號： S-7600A
廠商： Seiko Instruments Inc.
英文描述： Hardware Specification (TCP/IP Network Stack LSI)
中文描述： 硬件規(guī)格（TCP / IP網(wǎng)絡堆棧大規(guī)模集成電路）
文件頁數(shù)： 5/60頁
文件大?。?/td> 371K
代理商： S-7600A
TCP/IP Network Stack LSI
S-7600A
Hardware Specification
Revision 1.3
Seiko Instruments Inc.
iii
LIST OF FIGURES
F
IGURE
2-1
F
IGURE
3-1
F
IGURE
3-2
F
IGURE
3-3
F
IGURE
5-1
F
IGURE
5-2
F
IGURE
5-3
F
IGURE
5-4
F
IGURE
5-5
F
IGURE
5-6
F
IGURE
5-7
F
IGURE
6-1
F
IGURE
8-1
F
IGURE
9-1
F
IGURE
9-2
F
IGURE
10-1 E
XAMPLE FOR X
80 F
AMILY
MPU...................................................................................... 10-1
F
IGURE
10-2 E
XAMPLE FOR
68
K
F
AMILY
MPU...................................................................................... 10-2
F
IGURE
10-3 E
XAMPLE FOR
S
ERIAL
I
NTERFACE
.................................................................................... 10-3
B
LOCK
D
IAGRAM
............................................................................................................... 2-1
P
IN
A
SSIGNMENT
.............................................................................................................. 3-1
P
ACKAGE
D
IMENSIONS
...................................................................................................... 3-2
C
ONFIGURATION OF
E
ACH
P
IN
........................................................................................... 3-4
68
K
F
AMILY
MPU W
RITE
T
IMING
....................................................................................... 5-2
68
K
F
AMILY
MPU R
EAD
T
IMING
......................................................................................... 5-3
X
80 F
AMILY
MPU W
RITE
C
YCLE
T
IMING
............................................................................ 5-4
X
80 F
AMILY
MPU R
EAD
C
YCLE
T
IMING
.............................................................................. 5-5
S
ERIAL
I
NTERFACE
W
RITE
T
IMING
..................................................................................... 5-6
S
ERIAL
I
NTERFACE
R
EAD
T
IMING
....................................................................................... 5-7
INT1 I
NTERRUPT
T
IMING
................................................................................................... 5-8
M
EMORY
I
NTERFACE
A
RCHITECTURE
................................................................................. 6-1
S
ERIAL
D
ATA
F
ORMAT
....................................................................................................... 8-1
H
ARDWARE
R
ESET
T
IMING
................................................................................................ 9-1
S
OFTWARE
R
ESET
T
IMING
................................................................................................. 9-1
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