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參數(shù)資料
| 型號： | S-7600A |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | Hardware Specification (TCP/IP Network Stack LSI) |
| 中文描述： | 硬件規(guī)格（TCP / IP網(wǎng)絡堆棧大規(guī)模集成電路） |
| 文件頁數(shù)： | 34/60頁 |
| 文件大?。?/td> | 371K |
| 代理商： | S-7600A |
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TCP/IP Network Stack LSI
S-7600A
Hardware Specification
Revision 1.3
7-7
Seiko Instruments Inc.
Table 7-12
Conf Status Register Description
Bit
Bit Name
Access
Description
7
S_DAV
R/W
Serial Port Data Available
When read, bit indicates that Serial Port data is
available.
This bit should be written 0.
6
DCD
R/W
Carrier Detect
This bit reflects the current state of the
DCD
bit on
the serial port. It is independent of the
SCTL
bit
setting.
This bit should be written 0.
5
DSR / HWFC
R/W
Data Send Ready / Hardware Flow Control
When read, this bit reflects the current state of the
DSR
bit on the serial port.
When this bit written:
0 = Hardware Flow control is deactivated
1 = Hardware Flow control activated
Refer to Chapter 8 for more information about
Hardware Flow Control.
4
CTS
R
Clear To Send
This read-only bit reflects the current state of the
CTS
bit on the serial port. It is independent of the
SCTL
bit setting.
3
RI
R
Ring Indicator
This read-only bit reflects the current state of the
RI
bit on the serial port. It is independent of the
SCTL
bit setting.
2
DTR
R/W
Data Terminal Ready
Reading this bit follows the current state of the
DTR
bit on the serial port. The MPU can control the
DTR
by writing to this bit.
1
RTS
R/W
Request To Send
Reading this bit follows the current state of the
RTS
bit on the serial port. The MPU can control the
RTS
by writing to this bit.
0
SCTL
R/W
Serial Port Control
This bit determines who controls the serial port.
When this bit is low (default), the MPU controls the
port. When the
SCTL
bit is high, the network stack
controls the serial serial port.
0 = MPU controls serial port
1 = Hardware controls serial port
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