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| 型號(hào)： | S-7600A |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | Hardware Specification (TCP/IP Network Stack LSI) |
| 中文描述： | 硬件規(guī)格（TCP / IP網(wǎng)絡(luò)堆棧大規(guī)模集成電路） |
| 文件頁數(shù)： | 19/60頁 |
| 文件大?。?/td> | 371K |
| 代理商： | S-7600A |
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TCP/IP Network Stack LSI
S-7600A
Hardware Specification
Revision 1.3
Seiko Instruments Inc.
5-2
5.2.1. 68k Family MPU Mode
This mode can be selected by pulling the
C86
input pin “H” and the
PSX
input pin “H”. In this mode, the
address and data are muxed into a single 8-bit bus. All cycles start by placing an address on the bus and
setting the
RS
pin to “L”. In this mode
WRITEX
signal works as read/write(R/WX) signal and
READX
is
the enable(E) signal for 68k Family MPU interface. After the address cycle, the MPU generates a read or
writes strobe by setting the
READX
and
WRITEX
pins. The S-7600A MPU interface logic assert a
BUSYX
signal low during data write and read phases. The MPU samples the
BUSYX
signal before
starting a new cycle. The can initiate a new cycle if the bit is “H”.
5.2.1.1. Write Cycle Timing
Figure 5-1
68k Family MPU Write Timing
Symbol
T
CYC6
T
AH6
T
AW6
T
DS6
T
DH6
T
EW
T
BD6
T
BC6
T
BOD6
NOTES:
CLK is the clock of S-7600A
Timing is specified of 50% of the signal waveform.
Rise/fall time(20%,80%) of the input signal is 15nsec or less.
Table 5-3
68k Family MPU Write Cycle Timing
Description
System Cycle Time
Address Hold Time
Address Setup Time
Data Setup time
Data Hold Time
Enable Pulse Width
BUSYX Delay Time
BUSYX Pulse Width
BUSYX Output Disable Time
Min
100 ns
20ns
20ns
20ns
20 ns
40 ns
2CLK
Max
1.9CLK
30ns
30ns
Notes
CL=80pF
CL=80pF
CS
WRITEX
(R/WX)
CLK
BUSYX
READX
(E)
RS
SD7 to 0
T
AH6
T
AW6
T
DH6
T
DS6
T
BD6
T
BC6
T
DH6
T
AH6
T
AW6
T
CYC6
Address
T
EW
Data
T
DS6
T
EW
T
BOD6
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