參數(shù)資料
型號: S-7600A
廠商: Seiko Instruments Inc.
英文描述: Hardware Specification (TCP/IP Network Stack LSI)
中文描述: 硬件規(guī)格(TCP / IP網(wǎng)絡(luò)堆棧大規(guī)模集成電路)
文件頁數(shù): 31/60頁
文件大?。?/td> 371K
代理商: S-7600A
TCP/IP Network Stack LSI
S-7600A
Hardware Specification
Revision 1.3
Seiko Instruments Inc.
7-4
7.3. Register Definitions
7.3.1. Revision Register (0x00)
(Read-Only, Default 0x21)
This direct read-only register reports back the design revision. See the design revision form in Table 7-3
and Table 7-4.
Table 7-3
Revision Register Bit Definitions
Bit
7
6
5
4
3
2
1
0
Def.
Major Revision Number
Minor Revision Number
Default
0x2
0x1
Table 7-4
Revision Register Description
Bit
Bit Name
Access
Description
7:4
Major Revision
Number
R
This nibble indicates the major revision number for
the S-7600A core.
3:0
Minor Revision
Number
R
This nibble indicates the minor revision number for
the S-7600A core.
7.3.2. General Control Register (0x01)
(Read/Write, Default 0x00)
This direct register contains the master software reset. See the register format in Table 7-5 and Table
7-6.See the wave format in figure 9.-2.
Table 7-5
General Control Register Bit Definitions
Bit
7
6
5
4
3
2
1
0
Def.
SW_RST
Default
0
0
0
0
0
0
0
0
NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.
Table 7-6
General Control Register Description
Bit
Bit Name
Access
Description
0
SW_RST
R/W
Software Reset.
This active high reset returns the S-7600A core to
power-on reset settings. It is self-clearing and does
not need to be written to “0” for proper operations.
0 = Normal operation
1 = Soft reset
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