參數(shù)資料
型號: S-7600A
廠商: Seiko Instruments Inc.
英文描述: Hardware Specification (TCP/IP Network Stack LSI)
中文描述: 硬件規(guī)格(TCP / IP網(wǎng)絡(luò)堆棧大規(guī)模集成電路)
文件頁數(shù): 26/60頁
文件大?。?/td> 371K
代理商: S-7600A
TCP/IP Network Stack LSI
S-7600A
Hardware Specification
Revision 1.3
6-1
Seiko Instruments Inc.
6. Memory Requirements
6.1. Overview
S-7600A contains two general sockets along with the TCP/UDP/IP and PPP protocols. Their total
memory requirement is 10K bytes. This memory is included on the S-7600A chip.
6.2. Memory Interface Architecture
The Network Stack feeds all of its memory requests into a single Memory Arbiter inside of the Network
Stack core. The arbiter then feeds out one memory request to the SRAM interface. This interface serves
to translate the network stack's timing into signal timing required by the SRAM. This architecture is
shown in Figure 6-1.
TCP / UDP
IP
PPP
Network Stack
Serial Port
Memory
Arbiter
SRAM
Interface
SRAM
Figure 6-1
Memory Interface Architecture
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