參數(shù)資料
型號: S-7600A
廠商: Seiko Instruments Inc.
英文描述: Hardware Specification (TCP/IP Network Stack LSI)
中文描述: 硬件規(guī)格(TCP / IP網(wǎng)絡(luò)堆棧大規(guī)模集成電路)
文件頁數(shù): 28/60頁
文件大?。?/td> 371K
代理商: S-7600A
TCP/IP Network Stack LSI
S-7600A
Hardware Specification
Revision 1.3
7-1
Seiko Instruments Inc.
7. S-7600A Register Definitions
7.1. Overview
This section covers the S-7600A's API registers. The register are divided into three types: global, direct
and indexed.
Global registers occupy the address space from 0x00 to 0x1D and 0x60 to 0x6F. Direct and indexed
registers occupy the configuration space from 0x20 to 0x3F. Indexed register require the socket index to
be set prior to accessing the registers.
7.2. iAPI Register Map
Table 7-1 and Table 7-2 shows the complete iAPI register map for the S-7600A chip. All registers not
listed are reserved, and should not be accessed.
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