參數(shù)資料
型號: S-7600A
廠商: Seiko Instruments Inc.
英文描述: Hardware Specification (TCP/IP Network Stack LSI)
中文描述: 硬件規(guī)格(TCP / IP網(wǎng)絡(luò)堆棧大規(guī)模集成電路)
文件頁數(shù): 32/60頁
文件大?。?/td> 371K
代理商: S-7600A
TCP/IP Network Stack LSI
S-7600A
Hardware Specification
Revision 1.3
7-5
Seiko Instruments Inc.
7.3.3. Generic Socket Location Register (0x02)
(Read-Only)
This register is used to report back the location of general sockets to the software layer. Only bits [1:0] will
be set because the S-7600A chip is equipped with two general sockets.
Table 7-7
Generic Socket Location Register Bit Definitions
Bit
7
6
5
4
3
2
1
0
Def.
S7
S6
S5
S4
S3
S2
S1
S0
Value
0
0
0
0
0
0
1
1
Table 7-8
Generic Socket Location Register Description
Bit
Bit Name
Access
Description
7
S7
R
Not available
6
S6
R
Not available
5
S5
R
Not available
4
S4
R
Not available
3
S3
R
Not available
2
S2
R
Not available
1
S1
R
General socket 1 available
0
S0
R
General socket 0 available
7.3.4. Master Interrupt (0x04)
(Read-Only, Default 0x00)
This direct register indicates the source of the S-7600A interrupt.
Table 7-9
Master Interrupt Register Bit Definitions
Bit
7
6
5
4
3
2
1
0
Def.
PT_INT
LINK_INT
SOCK_INT
Default
0
0
0
0
0
0
0
0
NOTE: Reserved bits are signified by a dash (-). All Reserved bits should be written as “0”.
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