參數(shù)資料
型號(hào)： S-7600A
廠商： Seiko Instruments Inc.
英文描述： Hardware Specification (TCP/IP Network Stack LSI)
中文描述： 硬件規(guī)格（TCP / IP網(wǎng)絡(luò)堆棧大規(guī)模集成電路）
文件頁(yè)數(shù)： 3/60頁(yè)
文件大小： 371K
代理商： S-7600A
TCP/IP Network Stack LSI
S-7600A
Hardware Specification
Revision 1.3
Seiko Instruments Inc.
i
TABLE OF CONTENTS
1.
INTRODUCTION........................................................................................................................... 1-1
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
1.7.
P
RODUCT
O
VERVIEW
............................................................................................................... 1-1
F
EATURES
............................................................................................................................... 1-1
B
ENEFITS
................................................................................................................................. 1-1
T
RADEMARKS
........................................................................................................................... 1-2
D
EFINITIONS
............................................................................................................................ 1-2
A
PPLICABLE
D
OCUMENTS
......................................................................................................... 1-2
C
AUTIONS
................................................................................................................................ 1-2
2.
FUNCTIONAL BLOCK DIAGRAM ............................................................................................... 2-1
3.
TERMINALS.................................................................................................................................. 3-1
3.1.
3.2.
3.3.
3.4.
P
IN
A
SSIGNMENT
...................................................................................................................... 3-1
P
ACKAGE
D
IMENSIONS
............................................................................................................. 3-2
P
IN
D
ESCRIPTION
..................................................................................................................... 3-3
P
IN
C
ONFIGURATION
................................................................................................................ 3-4
4.
ELECTRICAL CHARACTERISTICS............................................................................................. 4-1
4.1.
4.2.
4.3.
4.4.
A
BSOLUTE
M
AXIMUM
R
ATINGS
.................................................................................................. 4-1
R
ECOMMENDED
O
PERATING
C
ONDITIONS
................................................................................. 4-1
DC C
HARACTERISTICS
............................................................................................................. 4-2
P
OWER
C
URRENT
C
ONSUMPTION
............................................................................................. 4-2
5.
MPU INTERFACE......................................................................................................................... 5-1
5.1.
5.2.
O
VERVIEW
............................................................................................................................... 5-1
P
ARALLEL
I
NTERFACE
............................................................................................................... 5-1
5.2.1.
68k Family MPU Mode.................................................................................................... 5-2
5.2.1.1.
Write Cycle Timing ................................................................................................................5-2
5.2.1.2.
Read Cycle Timing ................................................................................................................5-3
5.2.2.
x80 Family MPU Mode.................................................................................................... 5-4
5.2.2.1.
Write Cycle Timing ................................................................................................................5-4
5.2.2.2.
Read Cycle Timing ................................................................................................................5-5
5.3.
S
ERIAL
I
NTERFACE
................................................................................................................... 5-6
5.3.1.
Write Cycle Timing.......................................................................................................... 5-6
5.3.2.
Read Cycle Timing.......................................................................................................... 5-7
5.4.
I
NTERRUPT
............................................................................................................................... 5-8
6.
MEMORY REQUIREMENTS........................................................................................................ 6-1
6.1.
6.2.
6.3.
O
VERVIEW
............................................................................................................................... 6-1
M
EMORY
I
NTERFACE
A
RCHITECTURE
........................................................................................ 6-1
M
EMORY
M
AP
.......................................................................................................................... 6-2
7.
S-7600A REGISTER DEFINITIONS............................................................................................. 7-1
7.1.
7.2.
7.3.
O
VERVIEW
............................................................................................................................... 7-1
I
API R
EGISTER
M
AP
................................................................................................................. 7-1
R
EGISTER
D
EFINITIONS
............................................................................................................ 7-4
7.3.1.
Revision Register (0x00)................................................................................................ 7-4
7.3.2.
General Control Register (0x01).................................................................................... 7-4
7.3.3.
Generic Socket Location Register (0x02)...................................................................... 7-5
7.3.4.
Master Interrupt (0x04) .................................................................................................. 7-5
7.3.5.
Serial Port Configuration / Status Register (0x08)......................................................... 7-6
7.3.6.
Serial Port Interrupt Register (0x09).............................................................................. 7-8
7.3.7.
Serial Port Interrupt Mask Register (0x0A).................................................................... 7-8
7.3.8.
Serial Port Data Register (0x0B).................................................................................... 7-9
7.3.9.
BAUD Rate Divider Registers (0x0C-0x0D)................................................................... 7-9
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