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| 型號： | S-7600A |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | Hardware Specification (TCP/IP Network Stack LSI) |
| 中文描述： | 硬件規(guī)格（TCP / IP網(wǎng)絡(luò)堆棧大規(guī)模集成電路） |
| 文件頁數(shù)： | 35/60頁 |
| 文件大小： | 371K |
| 代理商： | S-7600A |
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TCP/IP Network Stack LSI
S-7600A
Hardware Specification
Revision 1.3
Seiko Instruments Inc.
7-8
7.3.6. Serial Port Interrupt Register (0x09)
(Read-Only, Default 0X000000B)
This register indicates the state of the serial port interrupt.
Table 7-13
Serial Port Interrupt Register Bit Definitions
Bit
7
6
5
4
3
2
1
0
Def.
PT_INT
Default
0
0
0
0
0
0
0
NOTE: Reserved bits are signified by a dash (-). All Reserved bits should be written as “0”.
Table 7-14
Serial Port Interrupt Register Description
Bit
Bit Name
Access
Description
7
PT_INT
R
Port Transport Interrupt
This bit indicates when the serial port interrupt is
active. This condition depends on the states of the
PINT_EN and DSINT_EN bits in the Serial Port
Interrupt Mask Register.
When PINT_EN is 1, an interrupt will occur
whenever data is available in the serial port input
FIFO ("S_DAV" in the Serial Port
Configuration/Status Register is 1).
When DSINT_EN is 1, an interrupt will be active
whenever the CPU can write to the Serial Port Data
Register to transmit a byte of data.
If both PINT_EN and DSINT_EN are enabled,
the interrupt will be active if either condition is met.
7.3.7. Serial Port Interrupt Mask Register (0x0A)
(Read/Write, Default 0x00)
This register enables the serial port interrupts. The default for this register is 0x00 (interrupts disabled).
Table 7-15
Serial Port Interrupt Mask Register Bit Definitions
Bit
7
6
5
4
3
2
1
0
Def.
PINT_EN
DSINT_EN
Default
0
0
0
0
0
0
0
0
NOTE: Reserved bits are signified by a dash (-). All Reserved bits should be written as “0”.
Table 7-16
Serial Port Interrupt Mask Register Description
Bit
Bit Name
Access
Description
7
PINT_EN
R/W
Port Interrupt Enable
This is the enable for the port interrupt.
6
DSINT_EN
R/W
Data sent interrupt Enable.
This is enable for the data sent interrupt.
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