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| 型號： | OR4E14 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 77/132頁 |
| 文件大小： | 2667K |
| 代理商： | OR4E14 |
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Lucent Technologies Inc.
77
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Special-Purpose Pins
(continued)
A[17:0]
MPI_BURST
MPI_BDIP
MPI_TSZ[1:0]
A[21:0]
MPI_ACK
I
During MPI mode, the A[17:0] are used as the address bus driven by the PowerPC bus
master utilizing the least significant bits of the PowerPC32-bit address.
During master parallel configuration mode, A[17:0] address the configuration EPROM. In
MPI mode, many of the A[n] pins have alternate uses as described below. See the special
function blocks section for more MPI information. During configuration, if not in master par-
allel or an MPI configuration mode, these pins are 3-stated with a pull-up enabled.
A[21] is used as the MPI_BURST. It is driven low to indicate a burst transfer is in progress.
Driven high indicates that the current transfer is not a burst.
A[22] is used as the MPI_BDIP It is driven by the PowerPCprocessor assertion of this pin
indicates that the second beat in front of the current one is requested by the master.
Negated before the burst transfer ends to abort the burst data phase.
A[19:18] are used as the MPI_TSZ[1:0] signals and are driven by the bus master to indicate
the data transfer size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word.
During master parallel mode A[21:0], address the configuration EPROMs up to 4M bytes.
If not used for MPI, these pins are user-programmable I/O pins.*
In PowerPCmode MPI operation, this is driven low indicating the MPI received the data on
the write cycle or returned data on a read cycle.
This is the PowerPCsynchronous, positive-edge bus clock used for the MPI interface. It can
be a source of the clock for the embedded system bus. If MPI is used, this can be the AMBA
bus clock.
A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on
the internal system bus for the current transaction.
This pin requests the MPC860 to relinquish the bus and retry the cycle.
I/O Selectable data bus width from 8, 16, 32-bit. Driven by the bus master in a write transaction.
Driven by MPI in a read transaction.
I
D[7:0] receive configuration data during master parallel, peripheral, and slave parallel con-
figuration modes and each pin has a pull-up enabled. During serial configuration modes, D0
is the DIN input.
D[7:3] output internal status for asynchronous peripheral mode when RD is low.
After configuration, the pins are user-programmable I/O pins.*
I/O Selectable parity bus width from 1, 2, 4-bit, DP[0] for D[7:0], DP[1] for D[15:8], DP[2] for
D[23:16], and DP[3] for D[32:24].
After configuration, this pin is a user-programmable I/O pin.*
I
During slave serial or master serial configuration modes, DIN accepts serial configuration
data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input.
During configuration, a pull-up is enabled.
I/O After configuration, this pin is a user-programmable I/O pin.*
O
During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained
slave devices. Data out on DOUT changes on the rising edge of CCLK.
I/OAfter configuration, DOUT is a user-programmable I/O pin.*
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pns (and the acti-
vation of all user I/Os) is controlled by a second set of options.
O
O
MPI_CLK
I
MPI_TEA
O
MPI_RTRY
D[31:0]
O
DP[3:0]
DIN
DOUT
Symbol
I/O
Description
Pin Information
(continued)
Table 42. Pin Descriptions
(continued)
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