參數(shù)資料
型號(hào): OR4E14
廠商: Lineage Power
英文描述: Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列)
中文描述: 現(xiàn)場(chǎng)可編程門陣列(現(xiàn)場(chǎng)可編程門陣列)
文件頁數(shù): 50/132頁
文件大?。?/td> 2667K
代理商: OR4E14
50
Lucent Technologies Inc.
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Embedded System Bus (ESB)
(continued)
Table 27. Embedded System Bus/MPI Registers
Table 28. Interrupt Register Space Assignments
Register
00
01
02
03
04
Byte
03—00
07—04
0B—08
0F—0C
13
12
11
10
17—14
1B—18
1F—1C
23—20
27—24
2B—28
2F—2C
33—30
37—34
3B—38
3F—3C
43—40
47—44
53—50
63—60
67—64
73—70
Read/Write
RO
R/W
R/W
RO
R/W
R/W
R/W
RO
R/W
RO
R/W
RO
RO
RO
RO
RO
RO
RO
RO
Initial Value
Description
32-bit device ID
Scratchpad register
Command register
Status register
Interrupt enable register—MPI
Interrupt enable register—USER
Interrupt enable register—FPSC
Interrupt cause register
Readback address register (14 bits)
Readback data register
Configuration data register
Reserved
Bus error address register
Interrupt vector 1 predefined by configuration bit stream
Interrupt vector 2 predefined by configuration bit stream
Interrupt vector 3 predefined by configuration bit stream
Interrupt vector 4 predefined by configuration bit stream
Interrupt vector 5 predefined by configuration bit stream
Interrupt vector 6 predefined by configuration bit stream
Top-left PPLL control/status
Top-left HPLL control/status
Top-right PPLL control/status
Bottom-left PPLL control/status
Bottom-left HPLL control/status
Bottom-right PPLL control/status
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
14
18
19
1C
Byte
13
12
11
10
Bit
7
0
7
0
7
0
Read/Write
R/W
R/W
R/W
Description
Interrupt enable register
MPI
Interrupt enable register
USER
Interrupt enable register—FPSC
Interrupt cause registers
USER_IRQ_GENERAL;
USER_IRQ_SLAVE;
USER_IRQ_MASTER;
CFG_IRQ_DATA;
ERR_FLAG 1
MPI_IRQ
FPSC_IRQ_SLAVE;
FPSC_IRQ_MASTER
7
6
5
4
3
2
1
0
RO
RO
RO
RO
RO
RO
RO
RO
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