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| 型號(hào)： | OR4E14 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門(mén)陣列) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列（現(xiàn)場(chǎng)可編程門(mén)陣列） |
| 文件頁(yè)數(shù)： | 31/132頁(yè) |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E14 |
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Lucent Technologies Inc.
31
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Routing Resources
The abundant routing resources of the Series 4 archi-
tecture are organized to route signals individually or as
buses with related control signals. Both local and global
signals utilize high-speed buffered and nonbuffered
routes. One PLC segmented (x1), six PLC segmented
(x6), and bused half-chip (xHL) routes are patterned
together to provide high connectivity with fast software
routing times and high-speed system performance.
x1 routes cross width of one PLC and provide local
connectivity to PFU and SLIC inputs and outputs. x6
lines cross width of six PLCs and are unidirectional and
buffered with taps in the middle and on the end. Seg-
ments allow connectivity to PFU/SLIC outputs (driven
at one endpoint), other x6 lines (at endpoints), and
x1 lines for access to PFU/SLIC inputs. xH lines run
vertically and horizontally the distance of half the
device and are useful for driving medium-/long-dis-
tance 3-state routing.
The improved routing resources offer great flexibility in
moving signals to and from the logic core. This flexibil-
ity translates into an improved capability to route
designs at the required speeds even when the I/O sig-
nals have been locked to specific pins.
Generally, the ORCA Foundry Development System is
used to automatically route interconnections. Interac-
tive routing with the ORCA Foundry design editor
(EPIC) is also available for design optimization.
The routing resources consist of switching circuitry and
metal interconnect segments. Generally, the metal lines
which carry the signals are designated as routing seg-
ments. The switching circuitry connects the routing
segments, providing one or more of three basic func-
tions: signal switching, amplification, and isolation. A
net running from a PFU or PIO output (source) to a
PLC or PIO input (destination) consists of one or more
routing segments, connected by switching circuitry
called configurable interconnect points (CIPs).
Clock Distribution Network
Primary Clock Nets
The Series 4 FPGAs provide eight fully distributed glo-
bal primary net routing resources. These eight primary
nets can only drive clock signals. The scheme dedi-
cates four of the eight resources to provide fast primary
nets and four are available for general primary nets.
The fast primary nets are targeted toward low-skew
and small injection times while the general primary
nets are also targeted toward low-skew but have more
source location flexibility. Fast access to the global pri-
mary nets can be sourced from two pairs of pads
located in the center of each side of the device, from
the programmable PLLs, and dedicated network PLLs
located in the corners, or from PLC logic. The I/O pads
are dedicated in pairs for use of differential I/O clocking
or single-ended I/O clock sources. However, if these
pads are not needed to source the clock network, they
can be utilized for general I/O. The clock routing
scheme is patterned using vertical and horizontal
routes which provide connectivity to all PLC columns.
Secondary Clock and Control Nets
Secondary spines provide flexible clocking and control
signaling for local regions. Secondary nets usually
have high fan-outs. The Series 4 utilizes a spine and
branches that use additional x6 segments. This strat-
egy provides a flexible connectivity and routes can be
sourced from any I/O pin, all PLLs, or from PLC logic.
Edge Clock Nets
Routes are distributed around the edges and are avail-
able for every four PIOs (one per PIC). All PIOs and
PLLs can drive the edge clocks and are used in con-
junction with the secondary spines discussed above to
drive the same edge clock signal into the internal logic
array. The edge clocks provide fast injection to the PLC
array and I/O registers. Many edge clock nets are pro-
vided on each side of the device.
Programmable Input/Output Cells
Programmable I/O
The Series 4 PIO addresses the demand for the flexi-
bility to select I/O that meets system interface require-
ments. I/Os can be programmed in the same manner
as in previous ORCA devices with the addition of new
features that allow the user the flexibility to select new I/
O types that support high-speed interfaces.
Each PIC contains up to four programmable I/O pads
and are interfaced through a common interface block to
the FPGA array. The PIO group is split into two pairs of
I/O pads with each pair having independent clock
enables, local set/reset, and global set/reset.
On the input side, each PIO contains a programmable
latch/FF which enables very fast latching of data from
any pad. The combination provides for very low setup
requirements and zero hold times for signals coming
on-chip. It may also be used to demultiplex an input sig-
nal, such as a multiplexed address/data signal, and
register the signals without explicitly building a demulti-
plexer with a PFU.
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