參數(shù)資料
型號: OR4E14
廠商: Lineage Power
英文描述: Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
中文描述: 現(xiàn)場可編程門陣列(現(xiàn)場可編程門陣列)
文件頁數(shù): 19/132頁
文件大?。?/td> 2667K
代理商: OR4E14
Lucent Technologies Inc.
19
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Programmable Logic Cells
(continued)
Memory Mode
The Series 4 PFU can be used to implement a 32 x 4 (128-bit) synchronous, dual-port RAM. A block diagram of a
PFU in memory mode is shown in Figure 12. This RAM can also be configured to work as a single-port memory
and because initial values can be loaded into the RAM during configuration, it can also be used as a ROM.
5-5969(F)a
1. CLK[0:1] are commonly connected in memory mode.
2. CE1 = write enable = wren; wren = 0 (no write enable); wren = 1 (write enabled).
CE0 = write port enable 0; CE0 = 0, wren = 0; CE0 = 1, wren = CE1.
LSR0 = write port enable 1; LSR0 = 0, wren = CE0; LSR0 = 1, wren = CE1.
Figure 12. Memory Mode
Q6
Q4
Q2
Q0
D
5
Q
CIN(WA1)
K
Z
[3:0]
4
F5[A:D]
D Q
DIN7(WA3)
D Q
DIN5(WA2)
D Q
DIN3(WA1)
D Q
DIN1(WA0)
D Q
DIN6(WD3)
D Q
DIN4(WD2)
D Q
DIN2(WD1)
D Q
DIN0(WD0)
D Q
CE0, LSR0
(SEE NOTE 2.)
S/E
CLK[0:1]
4
WRITE
DATA[3:0]
WRITE
ADDRESS[4:0]
READ
ADDRESS[4:0]
READ
4
F6
F4
F2
F0
D Q
D Q
D Q
D Q
WRITE
ENABLE
RAM CLOCK
DATA[3:0]
CE1
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