參數(shù)資料
型號(hào): OR4E14
廠商: Lineage Power
英文描述: Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列)
中文描述: 現(xiàn)場(chǎng)可編程門陣列(現(xiàn)場(chǎng)可編程門陣列)
文件頁數(shù): 40/132頁
文件大?。?/td> 2667K
代理商: OR4E14
40
Lucent Technologies Inc.
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Special Function Blocks
(continued)
5-6765(F)
Figure 26. Boundary-Scan Interface
D[7:0]
INTR
MICRO-
PROCESSOR
D[7:0]
CE
RA
R/W
DAV
INT
SP
TMS0
TCK
TDI
TDO
TDI
TMS
TCK
TDO
ORCA
SERIES
FPGA
TDI
ORCA
SERIES
FPGA
TMS
TCK
TDO
TDI
TMS
TCK
TDO
ORCA
SERIES
FPGA
LUCENT
BOUNDARY-
SCAN
MASTER
(BSM)
(DUT)
(DUT)
(DUT)
The boundary-scan support circuit shown in Figure 26
is the 497Aa boundary-scan master (BSM). The BSM
off-loads tasks from the test host to increase test
throughput. To interface between the test host and the
DUTs, the BSM has a general MPI and provides paral-
lel-to-serial/serial-to-parallel conversion, as well as
three 8K data buffers. The BSM also increases test
throughput with a dedicated automatic test-pattern
generator and with compression of the test response
with a signature analysis register. The PC-based
boundary-scan test card/software allows a user to
quickly prototype a boundary-scan test setup.
Boundary-Scan Instructions
The Series 4 boundary-scan circuitry includes ten
IEEE 1149.1, 1149.2, and 1532/D1 instructions and six
ORCA-defined instructions. These also include one
IEEE1149.3 optional instruction. A 6-bit wide instruc-
tion register supports all the instructions listed in
Table 22. The BYPASS instruction passes data inter-
nally from TDI to TDO after being clocked by TCK.
Table 22. Boundary-Scan Instructions
Code
000000
000001
000011
000100
000101
000110
001000
001001
001010
001011
001101
001110
010001
010010
010011
010100
010101
111111
Instruction
EXTEST
SAMPLE
PRELOAD
RUNBIST
IDCODE
USERCODE
ISC_ENABLE
ISC_PROGRAM
ISC_NOOP
ISC_DISABLE
ISC_PROGRAM_USERCODE
ISC_READ
PLC_SCAN_RING1
PLC_SCAN_RING2
PLC_SCAN_RING3
RAM_WRITE
RAM_READ
BYPASS
相關(guān)PDF資料
PDF描述
OR4E2 Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列)
OR4E4 Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列)
OR4E6 Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列)
ORT4622 Field-Programmable System Chip (FPSC) Four Channel x 622 Mbits/s Backplane Transceiver(現(xiàn)場(chǎng)可編程系統(tǒng)芯片(四通道x 622 M位/秒背板收發(fā)器))
ORT8850 Field-Programmable System Chip(現(xiàn)場(chǎng)可編程系統(tǒng)芯片)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR4E2 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable Gate Arrays
OR4E2-1BA256 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
OR4E2-1BA352 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
OR4E2-1BA416 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
OR4E2-1BC432 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA