參數(shù)資料
型號: OR4E14
廠商: Lineage Power
英文描述: Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
中文描述: 現(xiàn)場可編程門陣列(現(xiàn)場可編程門陣列)
文件頁數(shù): 67/132頁
文件大?。?/td> 2667K
代理商: OR4E14
Lucent Technologies Inc.
67
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
FPGA Configuration Modes
(continued)
5-5761(F)
Figure 41. PowerPC/MPI Configuration Schematic
Configuration readback can also be performed via the
MPI
when it is in user mode. The
MPI
is enabled in user
mode by setting the MPI_USER_ENABLE bit to 1 in the configuration control register prior to the start of configura-
tion or through a configuration option. To perform readback, the host processor writes the 14-bit readback start
address to the readback address registers and sets the
RD_CFG
bit to 0 in the configuration control register. Read-
back data is returned 8 bits at a time to the readback data register and is valid when the DATA_RDY bit of the status
register is 1. There is no error checking during readback. A flow chart of the
MPI
readback operation is shown in
Figure 43. The RD_DATA pin used for dedicated FPGA readback is invalid during
MPI
readback.
DOUT
CCLK
D[#:0]
A[17:0]
MPI_CLK
MPI_RW
MPI_ACK
MPI_BDIP
MPI_IRQ
MPI_STRB
CS0
CS1
HDC
LDC
D[#:0]
A[14:31]
CLKOUT
RD/WR
TA
BDIP
IRQx
TS
TO DAISY-
CHAINED
DEVICES
POWERPC
ORCA
SERIES 4
8, 16, 32
FPGA
DONE
INIT
BUS
CONTROLLER
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