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參數(shù)資料
| 型號： | OR4E14 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 49/132頁 |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E14 |
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Lucent Technologies Inc.
49
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Embedded System Bus (ESB)
Implemented using the open standard, on-chip bus AMBA-AHB 2.0 specification, the Series 4 devices connects all
the FPGA elements together with a standardized bus framework. The ESB facilitates communication among MPI,
configuration, EBRs, and user logic in all the generic FPGA devices. AHB serves the need for high-performance
SoC as well as aligning with current synthesis design flows. Multiple bus masters optimize system performance by
sharing resources between different bus masters such as the MPI and configuration logic. The wide data bus con-
figuration of 32 bits with 4-bit parity supports the high-bandwidth of data-intensive applications of using the wide on-
chip memory. AMBAenhances a reusable design methodology by defining a common backbone for IP modules.
The ESB is a synchronous bus that is driven by either the MPI clock, internal oscillator, CCLK (slave configuration
modes), TCK (JTAG configuration modes), or by a user clock from routing. During initial configuration and reconfig-
uration, the bus clock is defaulted to the configuration clock. The postconfiguration clock source is set during config-
uration. The user has the ability to program several slaves through the user logic interface. Embedded block RAM
also interfaces seamlessly to the AHB bus.
A single bus arbiter controls the traffic on the bus by ensuring that only one master has access to the bus at any
time. The arbiter monitors a number of different requests to use the bus and decides which request is currently the
highest priority. The configuration modes have the highest priority and overrides all normal user modes. Priority can
be programmed between MPI and user logic at configuration in generic FPGAs. If no priority is set, a round-robin
approach is used by granting the next requesting master in a rotating fixed order.
Several interfaces exist between the ESB and other FPGA elements. The MPI interface acts as a bridge between
the external microprocessor bus and ESB. The MPI may have different clock domains than the ESB if the ESB clock
is not sourced from the external microprocessor clock. Pipelined operation allows high-speed memory interface to
the EBR and peripheral access without the requirement for additional cycles on the bus. Burst transfers allow opti-
mal use of the memory interface by giving advance information of the nature of the transfers.
Table 27 is a listing of the ESB register file and brief descriptions. Table 28 shows the system interrupt registers and
Table 29 and Table 30 show the FPGA status and command registers, all with brief descriptions.
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| OR4E2-1BA352 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| OR4E2-1BA416 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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