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| 型號(hào)： | OR4E14 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門(mén)陣列) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列（現(xiàn)場(chǎng)可編程門(mén)陣列） |
| 文件頁(yè)數(shù)： | 52/132頁(yè) |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E14 |
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52
Lucent Technologies Inc.
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Phase-Locked Loops
There are eight PLLs available to perform many clock
modification and clock conditioning functions on the
Series 4 FPGAs. Six of the PLLs are programmable
allowing the user the flexibility to configure the PLL to
manipulate the frequency, phase, and duty cycle of a
clock signal. Four of the programmable PLLs are capa-
ble of manipulating and conditioning clocks from
20 MHz to 200 MHz and two others are capable of
manipulating and conditioning clocks from 60 MHz to
420 MHz. Frequencies can be adjusted from 1/8x to 8x
the input clock frequency. Each programmable PLL
provides two outputs that have different multiplication
factors with the same phase relationships. Duty cycles
and phase delays can be adjusted in 12.5% of the
clock period increments. An input buffer delay compen-
sation mode is available for phase delay. Each PPLL
provides two outputs (MCLK, NCLK) that can have pro-
grammable (12.5% steps) phase differences.
The PPLLs can be utilized to eliminate skew between
the clock input pad and the internal clock inputs across
the entire device. The PPLLs can drive onto the pri-
mary, secondary, and edge clock networks inside the
FPGA. Each PPLL can take a clock input from the ded-
icated pad or differential pair of pads in its corner or
from general routing resources.
Functionality of the PPLLs is programmed during oper-
ation through a read/write interface to the internal sys-
tem bus command and status registers or via the
configuration bit stream. There is also a PLL output sig-
nal, LOCK, that indicates a stable output clock state.
Unlike Series 3, this signal does not have to be inter-
grated before use.
Table 31. PPLL Specifications
Additional highly tuned and characterized dedicated phase-locked loops (DPLLs) are included to ease system
designs. These DPLLs meet ITU-T G.811 primary clocking specifications and enable system designers to target
very tightly specified clock conditioning not available in the universal PPLLs. DPLLs are targeted to low-speed net-
working DS1 and E1 and high-speed SONET/SDH networking STS-3 and STM-1 systems.
Parameter
Min
1.425
3.0
–40
1.425
1.425
20
60
20
60
30
45
—
—
—
—
—
Nom
1.5
3.3
25
1.5
1.5
—
—
—
—
—
50
28
8.5
30
<0.02
<50
Max
1.575
3.6
125
1.575
1.575
200
420
200
420
70
55
—
—
—
—
—
Unit
V
V
°C
V
V
MHz
V
DD
1.5
V
DD
3.3
Operating Temp
Input Clock Voltage
Output Clock Voltage
Input Clock Frequency
(no division)
Output Clock Frequency
PPLL
HPPLL
PPLL
HPPLL
MHz
Input Duty Cycle Tolerance
Output Duty Cycle
dc Power
Total On Current
Total Off Current
Cycle to Cycle Jitter (p-p)
Lock Time
Frequency Multiplication
Frequency Division
Duty Cycle Adjust of Output Clock
Delay Adjust of Output Clock
Phase Shift Between MCLK & NCLK
%
%
mW
mA
pA
UIp-p
μs
—
—
%
%
degree
1x, 2x, 3x, 4x, 5x, 6x, 7x, 8x,
1/8, 1/7, 1/6, 1/5, 1/4, 1/3, 1/2
12.5, 25, 37.5, 50, 62.5, 75, 87.5
0, 12.5, 25, 37.5, 50, 62.5, 75, 87.5
0, 45, 90, 135, 180, 225, 270, 315
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