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參數(shù)資料
| 型號(hào)： | OR4E14 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門(mén)陣列) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列（現(xiàn)場(chǎng)可編程門(mén)陣列） |
| 文件頁(yè)數(shù)： | 71/132頁(yè) |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E14 |
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Lucent Technologies Inc.
71
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
FPGA Configuration Modes
(continued)
5-4487(F)
Figure 45. Slave Parallel Configuration Schematic
Daisy Chaining
Multiple FPGAs can be configured by using a daisy chain of the FPGAs. Daisy chaining uses a lead FPGA and one
or more FPGAs configured in slave serial mode. The lead FPGA can be configured in any mode except slave paral-
lel mode. (Daisy chaining is available with the boundary-scan ram_w instruction discussed later.)
All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on
positive CCLK and out on negative CCLK edges.
An upstream FPGA that has received the preamble and length count outputs a high on DOUT until it has received
the appropriate number of data frames so that downstream FPGAs do not receive frame start bit pairs. After loading
and retransmitting the preamble and length count to a daisy chain of slave devices, the lead device loads its config-
uration data frames. The loading of configuration data continues after the lead device has received its configuration
data if its internal frame bit counter has not reached the length count. When the configuration RAM is full and the
number of bits received is less than the length count field, the FPGA shifts any additional data out on DOUT.
The configuration data is read into DIN of slave devices on the positive edge of CCLK, and shifted out DOUT on the
negative edge of CCLK. Figure 46 shows the connections for loading multiple FPGAs in a daisy-chain configura-
tion.
The generation of CCLK for the daisy-chained devices that are in slave serial mode differs depending on the config-
uration mode of the lead device. A master parallel mode device uses its internal timing generator to produce an
internal CCLK at eight times its memory address rate (RCLK). The asynchronous peripheral mode device outputs
eight CCLKs for each write cycle. If the lead device is configured in slave mode, CCLK must be routed to the lead
device and to all of the daisy-chained devices.
MICRO-
PROCESSOR
OR
SYSTEM
D[7:0]
DONE
INIT
CCLK
CS1
CS0
WR
M2
M1
M0
HDC
LDC
8
V
DD
PRGM
ORCA
FPGA
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| OR4E2 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable Gate Arrays |
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| OR4E2-1BA352 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| OR4E2-1BA416 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| OR4E2-1BC432 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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