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| 型號： | OR4E14 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 35/132頁 |
| 文件大小： | 2667K |
| 代理商： | OR4E14 |
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Lucent Technologies Inc.
35
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Programmable Input/Output Cells
(continued)
Table 15. PIO Options
Outputs
The PIO’s output drivers for TTL/CMOS outputs have
programmable drive capability and slew rates. Two
propagation delays (fast, slewlim) are available on out-
put drivers. There are three combinations of program-
mable drive currents (24 mA sink/12 mA source, 12 mA
sink/6 mA, and 6 mA sink/3 mA source). At powerup,
the output drivers are in slewlim mode and
12 mA sink/6 mA source. If an output is not to be driven
in the selected configuration mode, it is 3-stated.
The output buffer signal can be inverted, and the
3-state control signal can be made active-high, active-
low, or always enabled. In addition, this 3-state signal
can be registered or nonregistered. Additionally, there
is a fast, open-drain output option that directly connects
the output signal to the 3-state control, allowing the out-
put buffer to either drive to a logic 0 or 3-state, but
never to drive to a logic 1.
The PIO has both input and output shift register capa-
bilities. This ability allows the data rate to be reduced
from the pad or increased to the pad by two or four
times. The shift register block (SRB) is available in
groups of four PIO. Both the input and output shift reg-
isters are controlled by the same clock and can operate
at the same time at the same speed as long as the
SRB is not connected to the same pads.The output
control signals are similar to the input control signals in
that they are per pair of PIOs.
Bus Hold
Each PIO can be programmed with a KEEPERMODE
feature. This element is user programmed for bus hold
requirements. This mode retains the last known state of
a bus when the bus goes into 3-state. It prevents float-
ing buses and saves system power.
PIO Register Control Signals
The PIO latches/FFs have various clock, clock enable
(CE), local set/reset (LSR), and GSRN controls. Table
16 provides a summary of these control signals and
their effect on the PIO latches/FFs. Note that all control
signals are optionally invertible. The output control sig-
nals are similar to the input control signals in that they
are per pair of PIOs.
Table 16. PIO Register Control Signals
Input
Option
Input Level
LVTTL, LVCMOS 2,
LVCMOS 1.8, 3.3 V PCI Compliant.
Fast, Delayed.
Pull-up, Pull-down, None.
Latch, FF, Fast Zero Hold FF, None
(direct input).
Inverted, Noninverted.
Input 1, Input 2, Clock Input.
On, Off.
Input Speed
Float Value
Register Mode
Clock Sense
Input Selection
Keeper Mode
LVDS Resistor
On, Off.
Output
Output Drive
Current
Output Function Normal, Fast Open Drain.
Output Speed
Fast, Slew.
Output Source
FF Direct-out, General Routing.
Output Sense
Active-high, Active-low.
3-State Sense
Active-high, Active-low (3-state).
FF Clocking
Edge Clock, System Clock.
Clock Sense
Inverted, Noninverted.
Logic Options
See Table 17.
Option
12 mA/6 mA or 6 mA/3 mA
24 mA/12 mA.
I/O Controls
Clock Enable
Option
Active-high, Active-low, Always
Enabled.
Active-high, Active-low, No Local
Reset.
Synchronous, Asynchronous.
Set/Reset Level
Set/Reset Type
Set/Reset Priority CE over LSR, LSR over CE.
GSR Control
Enable GSR, Disable GSR.
Control Signal
Edge Clock
(ECLK)
Effect/Functionality
Clocks input fast-capture latch;
optionally clocks output FF, or
3-state FF.
Clocks input latch/FF; optionally
clocks output FF, or 3-state FF.
Optionally enables/disables input FF
(not available for input latch mode);
optionally enables/disables output
FF; separate CE inversion capability
for input and output.
Option to disable; affects input latch/
FF, output FF, and 3-state FF if
enabled.
Option to enable or disable per PIO
(the input FF, output FF, and
3-state FF) after initial configuration.
Set/Reset Mode The input latch/FF, output FF, and
3-state FF are individually set or
reset by both the LSR and GSRN
inputs.
System Clock
(SCLK)
Clock Enable
(CE)
Local Set/Reset
(LSR)
Global Set/Reset
(GSRN)
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