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參數(shù)資料
| 型號： | ORT8850 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable System Chip(現(xiàn)場可編程系統(tǒng)芯片) |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（現(xiàn)場可編程系統(tǒng)芯片） |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 153K |
| 代理商： | ORT8850 |
Preliminary Product Brief
May 2000
ORCA
ORT8850
Field-Programmable System Chip
Introduction
Field-programmable system chips (FPSCs) bring a
whole new dimension to programmable logic: FPGA
logic and an embedded system solution on a single
device. Lucent Technologies Microelectronics Group
has developed a solution for designers who need the
many advantages of FPGA-based design implemen-
tation, coupled with high-speed serial backplane data
transfer. Built on the Series 4 reconfigurable embed-
ded system-on-chips (SoC) architecture, the
ORT8850 family are backplane transceivers contain-
ing eight channels, each operating at up to
850 Mbits/s (6.8 Gbits/s when all eight channels are
used) full-duplex synchronous interface with built-in
clock and data recovery (CDR) in standard-cell logic,
along with up to 260K usable FPGA system gates.
The CDR circuitry is a macrocell available from
Lucent's Silicon Suite’s
macro library, and has
already been implemented in numerous applications
including ASICs, standard products, and FPSCs to
create interfaces for SONET/SDH STS-3/STM-1,
STS-12/STM-4, STS-48/STM-16, and STS-192/
STM-64 applications. With the addition of protocol
and access logic such as protocol-independent fram-
ers, asynchronous transfer mode (ATM) framers,
packet-over-SONET (POS) interfaces, and framers
for HDLC for Internet Protocol (IP), designers can
build a configurable interface retaining proven back-
plane driver/receiver technology. Designers can also
use the device to drive high-speed data transfer
across buses within a system that are not SONET/
SDH based. For example, designers can build a 6.8
Gbits/s PCI-to-PCI half bridge using our PCI soft
core.
The ORT8850 offers a clockless, high-speed inter-
face for interdevice communication on a board or
across a backplane. The built-in clock recovery of the
ORT8850 allows for higher system performance,
easier-to-design clock domains in a multiboard sys-
tem, and fewer signals on the backplane. Network
designers will benefit from the backplane transceiver
as a network termination device. The backplane
transceiver offers SONET scrambling/descrambling
of data and streamlined SONET framing, pointer
moving and transport overhead handling, plus the
programmable logic to terminate the network into
proprietary systems. For non-SONET application, all
SONET functionality is hidden from the user and no
prior networking knowledge is required.
Also included on the device are three full-duplex
high-speed parallel interfaces, consisting of 8-bit
data, control (such as start-of-cell), and clock. The
interface delivers double data rate (DDR) data at
rates up to 311 MHz (622 Mbits/s per pin), and con-
verts this data internal to the device into 32-bit wide
data running at half rate on one clock edge. Func-
tions such as centering the transmit clock in the
transmit data eye are done automatically by the inter-
face. Applications delivered by this interface include
the recently proposed RapidIO* packet-based inter-
face.
* RapidIO is a trademark of Motorola, Inc.
Table 1. ORCA ORT8850 Family—Available FPGA Logic
The embedded core and interface are not included in the above gate counts.The usable gate counts range from a logic-only gate count
to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as
108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIO
groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used as RAM are counted at
four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Embedded block RAM (EBR) is
counted as four gates per bit plus each block has an additional 25 K gates. 7 K gates are used for each PLL and 50K gates for the
embedded system bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in the gate count calcula-
tions.
Device
PFU
Rows
26
46
PFU
Columns
24
44
Total
PFUs
624
2024
User I/O
LUTs
EBR
Blocks
8
16
EBR Bits
(K)
74
147
Usable
Gates (K)
260—470
530—970
ORT8850L
ORT8850H
TBD
TBD
4992
16,192
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ORT8850-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT8850H | 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| ORT8850H-1BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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