參數(shù)資料
型號： NAND512W3A2SN6E
元件分類： PROM
英文描述： 64M X 8 FLASH 3V PROM, PDSO48
封裝： 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件頁數(shù)： 7/51頁
文件大?。?/td> 1009K
代理商： NAND512W3A2SN6E
Numonyx SLC SP 70 nm
Bus operations
210403 - Rev 3
4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see Table 6: Bus operations, for a summary.
4.1
Command input
Command input bus operations are used to give commands to the memory. Command are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 18 and Table 21 for details of the timings requirements.
4.2
Address input
Address input bus operations are used to input the memory address. Four bus cycles are
required to input the addresses for the 512 Mbit devices (refer to Table 7 and Table 8,
Address Insertion).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See Figure 19 and Table 21 for details of the timings requirements.
4.3
Data input
Data Input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See Figure 20, Table 21, and Table 22 for details of the timings requirements.
4.4
Data output
Data Output bus operations are used to read: the data in the memory array, the status
register, the electronic signature and the serial number.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is
Low, and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
See Figure 21 and Table 22 for details of the timings requirements.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NAND512W3A2SN6F 制造商:Micron Technology Inc 功能描述:512MB NAND FLASH 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel
NAND512W3A2SZA6E 制造商:Micron Technology Inc 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA Tray 制造商:Micron Technology Inc 功能描述:NAND - Trays 制造商:Micron Technology Inc 功能描述:MICNAND512W3A2SZA6E 512MB NAND FLASH 制造商:Micron Technology 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA Tray
NAND512W3A2SZA6F 制造商:Micron Technology Inc 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA T/R 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel 制造商:Micron Technology 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA T/R
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NAND512W4A0AZA6E 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL 3V/3.3V 512MBIT 32MX16 12US 63VFBGA - Trays
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