參數(shù)資料
型號(hào)： NAND512W3A2SN6E
元件分類： PROM
英文描述： 64M X 8 FLASH 3V PROM, PDSO48
封裝： 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件頁(yè)數(shù)： 10/51頁(yè)
文件大小： 1009K
代理商： NAND512W3A2SN6E
Command set
Numonyx SLC SP 70 nm
210403 - Rev 3
5
Command set
All bus write operations to the device are interpreted by the command interface. The
commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is High. Device operations are selected by writing
specific commands to the command register. The two-step command sequences for
program and erase operations are imposed to maximize data security.
The commands are summarized in Table 10.
Table 10.
Commands
Command
Bus write operations(1)(2)
1.
The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or
input/output data are not shown.
2.
Any undefined command sequence is ignored by the device.
Command
accepted during
busy
1st cycle
2nd cycle
3rd cycle
Read A
00h
–
Read B(3)
3.
The Read B command (code 01h) is not used in x16 devices.
01h
–
Read C
50h
–
Read Electronic Signature
90h
–
Read Status Register
70h
–
Yes
Page Program
80h
10h
–
Copy Back Program
00h
8Ah
(10h)(4)
4.
The Program Confirm command (code 10h) is no more necessary for 512 Mbit, 70 nm devices. It is
optional and has been maintained for backward compatibility.
Block Erase
60h
D0h
–
Reset
FFh
–
Yes
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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