參數(shù)資料
型號(hào)： NAND512W3A2SN6E
元件分類： PROM
英文描述： 64M X 8 FLASH 3V PROM, PDSO48
封裝： 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件頁數(shù)： 16/51頁
文件大?。?/td> 1009K
代理商： NAND512W3A2SN6E
Numonyx SLC SP 70 nm
Device operations
210403 - Rev 3
6.3
Page program
The page program operation is the standard operation to program data to the memory array.
The main area of the memory array is programmed by page, however partial page
programming is allowed where any number of Bytes (1 to 528) or Words (1 to 264) can be
programmed.
The maximum number of consecutive partial page program operations allowed in the same
page is three. After exceeding this a Block Erase command must be issued before any
further program operations can take place in that page.
Before starting a page program operation a pointer operation can be performed to point to
the area to be programmed. Refer to the Section 6.1: Pointer operations and Figure 7 for
details.
Each page program operation consists of five steps (see Figure 12):
1.
One bus cycle is required to setup the Page Program command
2.
Four bus cycles are then required to input the program address (refer to Table 7 and
3.
The data is then input (up to 528 Bytes/264 Words) and loaded into the page buffer
4.
One bus cycle is required to issue the confirm command to start the P/E/R controller
5.
The P/E/R controller then programs the data into the array.
Once the program operation has started the status register can be read using the Read
Status Register command. During program operations the status register only flags errors
for bits set to '1' that have not been successfully programmed to '0'.
During the program operation, only the Read Status Register and Reset commands are
accepted, all other commands are ignored.
Once the program operation has completed the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High.
The device remains in read status register mode until another valid command is written to
the command interface.
Figure 12.
Page program operation
1.
Before starting a page program operation a pointer operation can be performed. Refer to Section 6.1: Pointer operations for
details.
I/O
RB
Address Inputs
SR0
ai07566
Data Input
10h
70h
80h
Page Program
Setup Code
Confirm
Code
Read Status Register
Busy
tBLBH2
(Program Busy time)
相關(guān)PDF資料
PDF描述
NAND99R3M2AZBB5E SPECIALTY MEMORY CIRCUIT, PBGA107
NAND99W3M1AZBC5F SPECIALTY MEMORY CIRCUIT, PBGA137
NANDB9R4N2BZBA5F SPECIALTY MEMORY CIRCUIT, PBGA149
NANDBAR4N1BZBC5F SPECIALTY MEMORY CIRCUIT, PBGA137
NANDB9R4N2CZBA5E SPECIALTY MEMORY CIRCUIT, PBGA149
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NAND512W3A2SN6F 制造商:Micron Technology Inc 功能描述:512MB NAND FLASH 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel
NAND512W3A2SZA6E 制造商:Micron Technology Inc 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA Tray 制造商:Micron Technology Inc 功能描述:NAND - Trays 制造商:Micron Technology Inc 功能描述:MICNAND512W3A2SZA6E 512MB NAND FLASH 制造商:Micron Technology 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA Tray
NAND512W3A2SZA6F 制造商:Micron Technology Inc 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA T/R 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel 制造商:Micron Technology 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA T/R
NAND512W4A0AN6E 功能描述:閃存 NAND & S.MEDIA FLASH RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
NAND512W4A0AZA6E 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL 3V/3.3V 512MBIT 32MX16 12US 63VFBGA - Trays
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*