參數(shù)資料
型號： NAND512W3A2SN6E
元件分類： PROM
英文描述： 64M X 8 FLASH 3V PROM, PDSO48
封裝： 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件頁數(shù)： 29/51頁
文件大小： 1009K
代理商： NAND512W3A2SN6E
Numonyx SLC SP 70 nm
DC and AC parameters
210403 - Rev 3
Table 20.
DC characteristics, 3 V devices(1)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
IDD1
Operating current
Sequential
read
tRLRL minimum
E =VIL, IOUT =0mA
–10
20
mA
IDD2
Program
–
10
20
mA
IDD3
Erase
–
10
20
mA
IDD4
Standby current (TTL)
E=VIH, WP=0V/VDD
–
1
mA
IDD5
Standby current (CMOS)
E=VDD-0.2, WP=0/VDD
–
10
50
A
ILI
Input leakage current
VIN= 0 to VDDmax
–
±10
A
ILO
Output leakage current
VOUT= 0 to VDDmax
–
±10
A
VIH
Input high voltage
–
2.0
–
VDD+0.3
V
VIL
Input low voltage
–
0.3
–
0.8
V
VOH
Output high voltage level
IOH = 400 A
2.4
–
V
VOL
Output low voltage level
IOL = 2.1 mA
–
0.4
V
IOL (RB)
Output low current (RB)
VOL = 0.4 V
8
10
mA
VLKO
VDD supply voltage (erase and
program lockout)
–
1.5
V
1.
Standby and leakage currents refer to a single die device. For a multiple die device, their value must be multiplied for the
number of dice of the stacked device, while the active power consumption depends on the number of dice concurrently
executing different operations.
Table 21.
AC characteristics for command, address, data input
Symbol
Alt.
symbol
Parameter
1.8 V
devices
3 V
devices
Unit
tALLWH
tALS
Address Latch Low to Write Enable High
AL setup time
Min
25
15
ns
tALHWH
Address Latch High to Write Enable High
tCLHWH
tCLS
Command Latch High to Write Enable High
CL setup time
Min
25
15
ns
tCLLWH
Command Latch Low to Write Enable High
tDVWH
tDS
Data Valid to Write Enable High
Data setup time
Min
20
15
ns
tELWH
tCS
Chip Enable Low to Write Enable High
E setup time
Min
30
20
ns
tWHALH
tALH
Write Enable High to Address Latch High
AL hold time
Min
10
5
ns
tWHALL
Write Enable High to Address Latch Low
tWHCLH
tCLH
Write Enable High to Command Latch High
CL hold time
Min
10
5
ns
tWHCLL
Write Enable High to Command Latch Low
tWHDX
tDH
Write Enable High to Data Transition
Data hold time
Min
10
5
ns
tWHEH
tCH
Write Enable High to Chip Enable High
E hold time
Min
10
5
ns
tWHWL
tWH
Write Enable High to Write Enable Low
W High hold
time
Min
15
10
ns
tWLWH
tWP
Write Enable Low to Write Enable High
W pulse width
Min
25
15
ns
tWLWL
tWC
Write Enable Low to Write Enable Low
Write cycle time
Min
45
30
ns
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