參數(shù)資料
型號(hào)： NAND512W3A2SN6E
元件分類： PROM
英文描述： 64M X 8 FLASH 3V PROM, PDSO48
封裝： 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件頁(yè)數(shù)： 6/51頁(yè)
文件大?。?/td> 1009K
代理商： NAND512W3A2SN6E
Signal descriptions
Numonyx SLC SP 70 nm
210403 - Rev 3
R
Input
The Read Enable, R, controls the sequential data output
during read operations. Data is valid tRLQV after the falling
edge of R. The falling edge of R also increments the
internal column address counter by one.
W
Input
The Write Enable input, W, controls writing to the
command interface, input address and data latches. Both
addresses and data are latched on the rising edge of Write
Enable.
During power-up and power-down a recovery time of 10 s
(min) is required before the command interface is ready to
accept a command. It is recommended to keep Write
Enable High during the recovery time.
WP
Input
The Write Protect pin is an input that gives a hardware
protection against unwanted program or erase operations.
When Write Protect is Low, VIL, the device does not accept
any program or erase operations.
It is recommended to keep the Write Protect pin Low, VIL,
during power-up and power-down.
RB
Output
The Ready/Busy output, RB, is an open-drain output that
can be used to identify if the P/E/R controller is currently
active.
When Ready/Busy is Low, VOL, a read, program or erase
operation is in progress. When the operation completes
Ready/Busy goes High, VOH.
The use of an open-drain output allows the Ready/Busy
pins from several memories to be connected to a single
pull-up resistor. A Low will then indicate that one, or more,
of the memories is busy.
During power-up and power-down a recovery time of 10 s
(min) is required before the command interface is ready to
accept a command. During the recovery time the RB signal
is Low, VOL.
characteristics for details on how to calculate the value of
the pull-up resistor.
Supply
VDD
Supply voltage
VDD provides the power supply to the internal core of the
memory device. It is the main power supply for all
operations (read, program and erase).
An internal voltage detector disables all functions
whenever VDD is below the VLKO threshold (see Figure 34:
Data protection) to protect the device from any involuntary
program/erase operations during power-transitions.
VSS
Ground
Ground, VSS, is the reference for the power supply. It must
be connected to the system ground.
Table 5.
Signal descriptions (continued)
Symbol
Type
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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