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參數(shù)資料
| 型號： | NAND512W3A2SN6E |
| 元件分類： | PROM |
| 英文描述： | 64M X 8 FLASH 3V PROM, PDSO48 |
| 封裝： | 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48 |
| 文件頁數(shù)： | 19/51頁 |
| 文件大?。?/td> | 1009K |
| 代理商： | NAND512W3A2SN6E |
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Device operations
Numonyx SLC SP 70 nm
210403 - Rev 3
6.7
Read status register
The device contains a status register which provides information on the current or previous
program or erase operation. The various bits in the status register convey information and
errors on the operation.
The status register is read by issuing the Read Status Register command. The status
register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enable or Read Enable, whichever occurs last. When several memories are connected in a
system, the use of Chip Enable and Read Enable signals allows the system to poll each
device separately, even when the Ready/Busy pins are common-wired. It is not necessary
to toggle the Chip Enable or Read Enable signals to update the contents of the status
register.
After the Read Status Register command has been issued, the device remains in read
status register mode until another command is issued. Therefore if a Read Status Register
command is issued during a random read cycle a new read command must be issued to
continue with a page read.
The status register bits are summarized in Table 12: Status register bits. Refer to Table 12 in
conjunction with the following text descriptions.
6.7.1
Write protection bit (SR7)
The write protection bit can be used to identify if the device is protected or not. If the write
protection bit is set to ‘1’ the device is not protected and program or erase operations are
allowed. If the write protection bit is set to ‘0’ the device is protected and program or erase
operations are not allowed.
6.7.2
P/E/R controller bit (SR6)
The program/erase/read controller bit indicates whether the P/E/R controller is active or
inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R controller is active (device is
busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is ready).
6.7.3
Error bit (SR0)
The error bit is used to identify if any errors have been detected by the P/E/R controller. The
error bit is set to ’1’ when a program or erase operation has failed to write the correct data to
the memory. If the error bit is set to ‘0’ the operation has completed successfully.
6.7.4
SR5, SR4, SR3, SR2 and SR1 are reserved
Table 12.
Status register bits
Bit
Name
Logic level
Definition
SR7
Write protection
'1'
Not protected
'0'
Protected
SR6
Program/ erase/ read controller
'1'
P/E/R C inactive, device ready
'0'
P/E/R C active, device busy
SR5, SR4, SR3, SR2, SR1
Reserved
Don’t care
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| NAND512W3A2SN6F | 制造商:Micron Technology Inc 功能描述:512MB NAND FLASH 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel |
| NAND512W3A2SZA6E | 制造商:Micron Technology Inc 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA Tray 制造商:Micron Technology Inc 功能描述:NAND - Trays 制造商:Micron Technology Inc 功能描述:MICNAND512W3A2SZA6E 512MB NAND FLASH 制造商:Micron Technology 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA Tray |
| NAND512W3A2SZA6F | 制造商:Micron Technology Inc 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA T/R 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel 制造商:Micron Technology 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA T/R |
| NAND512W4A0AN6E | 功能描述:閃存 NAND & S.MEDIA FLASH RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| NAND512W4A0AZA6E | 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL 3V/3.3V 512MBIT 32MX16 12US 63VFBGA - Trays |
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