參數(shù)資料
型號(hào): NAND512W3A2SN6E
元件分類: PROM
英文描述: 64M X 8 FLASH 3V PROM, PDSO48
封裝: 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件頁(yè)數(shù): 15/51頁(yè)
文件大?。?/td> 1009K
代理商: NAND512W3A2SN6E
Device operations
Numonyx SLC SP 70 nm
210403 - Rev 3
Figure 9.
Sequential row read operations
Figure 10.
Sequential row read block diagrams
Figure 11.
Read block diagrams
1.
Highest address depends on device density.
I/O
RB
Address Inputs
ai07597
1st
Page Output
Busy
tBLBH1
(Read Busy time)
00h/
01h/ 50h
Command
Code
2nd
Page Output
Nth
Page Output
Busy
tBLBH1
AI07598
Block
Area A
(1st half Page)
Read A Command, x8 Devices
Area B
(2nd half Page)
Area C
(Spare)
Area A
(main area)
Area C
(Spare)
Read A Command, x16 Devices
Read B Command, x8 Devices
Read C Command, x8/x16 Devices
Area A
Area A/ B
Area C
(Spare)
Area A
(1st half Page)
Area B
(2nd half Page)
Area C
(Spare)
1st page
2nd page
Nth page
1st page
2nd page
Nth page
1st page
2nd page
Nth page
1st page
2nd page
Nth page
Block
AI07596
A0-A7
A9-A26(1)
Area A
(1st half page)
Read A command, x8 devices
Area B
(2nd half page)
Area C
(spare)
Area A
(main area)
Area C
(spare)
A0-A7
Read A command, x16 devices
A0-A7
Read B command, x8 devices
Area A
(1st half page)
Area B
(2nd half page)
Area C
(spare)
A0-A3 (x 8)
A0-A2 (x 16)
Read C command, x8/x16 devices
Area A
Area A/ B
Area C
(spare)
A9-A26(1)
A4-A7 (x 8), A3-A7 (x 16) are don't care
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