參數(shù)資料
型號(hào)： NAND512W3A2SN6E
元件分類： PROM
英文描述： 64M X 8 FLASH 3V PROM, PDSO48
封裝： 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件頁(yè)數(shù)： 18/51頁(yè)
文件大?。?/td> 1009K
代理商： NAND512W3A2SN6E
Numonyx SLC SP 70 nm
Device operations
210403 - Rev 3
6.5
Block erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of three steps (refer to Figure 14):
1.
One bus cycle is required to setup the Block Erase command
2.
Only three bus cycles are required to input the block address. The first cycle (A0 to A7)
is not required as only addresses A14 to A25 are valid, A9 to A13 are ignored. In the
last address cycle I/O2 to I/O7 must be set to VIL.
3.
One bus cycle is required to issue the Confirm command to start the P/E/R controller.
Once the erase operation has completed the status register can be checked for errors.
Figure 14.
Block erase operation
6.6
Reset
The Reset command is used to reset the command interface and status register. If the
Reset command is issued during any operation, the operation will be aborted. If it was a
program or erase operation that was aborted, the contents of the memory locations being
modified will no longer be valid as the data will be partially programmed or erased.
If the device has already been reset then the new Reset command will not be accepted.
The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value
of tBLBH4 depends on the operation that the device was performing when the command was
issued, refer to Table 22 for the values.
I/O
RB
Block Address
Inputs
SR0
ai07593
D0h
70h
60h
Block Erase
Setup Code
Confirm
Code
Read Status Register
Busy
tBLBH3
(Erase Busy time)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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