參數(shù)資料
型號: MC68EC060RC50
廠商: Freescale Semiconductor
文件頁數(shù): 90/128頁
文件大?。?/td> 0K
描述: IC MPU 32BIT 50MHZ 206-PGA
標準包裝: 10
系列: M680x0
處理器類型: M680x0 32-位
速度: 50MHz
電壓: 3.3V
安裝類型: 通孔
封裝/外殼: 206-BEPGA
供應(yīng)商設(shè)備封裝: 206-PGA(47.25x47.25)
包裝: 托盤
Signal Description
2-18
M68060 USER’S MANUAL
MOTOROLA
Table 2-8. Signal Summary
Signal Name
Mnemonic
Input/
Output
Active
State
Three-State
Reset
State
Address Bus
A31–A0
Input/Output
High
Yes
Three-Stated
Cycle Long-Word Address
CLA
Input
Low
Data Bus
D31–D0
Input/Output
High
Yes
Three-Stated
Transfer Type 1
TT1
Input/Output
High
Yes
Three-Stated
Transfer Type 0
TT0
Output
High
Yes
Three-Stated
Transfer Modifier
TM2–TM0
Output
High
Yes
Three-Stated
Transfer Line Number
TLN1,TLN0
Output
High
Yes
Three-Stated
User-Programmable Attributes
UPA1,UPA0
Output
High
Yes
Three-Stated
Read/Write
R/W
Output
High/Low
Yes
Three-Stated
Transfer Size
SIZ1,SIZ0
Output
High
Yes
Three-Stated
Bus Lock
LOCK
Output
Low
Yes
Three-Stated
Bus Lock End
LOCKE
Output
Low
Yes
Three-Stated
Cache Inhibit Out
CIOUT
Output
Low
Yes
Three-Stated
Byte Select
BS3–BS0
Output
Low
Yes
Three-Stated
Transfer Start
TS
Input/Output
Low
Yes
Three-Stated
Transfer in Progress
TIP
Output
Low
Yes
Three-Stated
Starting Termination Acknowledge Signal Sampling
SAS
Output
Low
Yes
Three-Stated
Transfer Acknowledge
TA
Input
Low
Transfer Retry Acknowledge
TRA
Input
Low
Transfer Error Acknowledge
TEA
Input
Low
Transfer Burst Inhibit
TBI
Input
Low
Transfer Cache Inhibit
TCI
Input
Low
Snoop Control
SNOOP
Input
Low
Bus Request
BR
Output
Low
No
Negated
Bus Grant
BG
Input
Low
Bus Grant Relinquish Control
BGR
Input
Low
Bus Busy
BB
Input/Output
Low
Yes
Three-Stated
Bus Tenure Termination
BTT
Input/Output
Low
Yes
Three-Stated
Cache Disable
CDIS
Input
Low
MMU Disable
MDIS
Input
Low
Reset In
RSTI
Input
Low
Reset Out
RSTO
Output
Low
No
Negated
Interrupt Priority Level
IPL2–IPL0
Input
Low
Interrupt Pending
IPEND
Output
Low
No
Negated
Autovector
AVEC
Input
Low
Processor Status
PST4–PST0
Output
High
No
10000
Processor Clock
CLK
Input
Clock Enable
CLKEN
Input
Low
JTAG Enable
JTAG
Input
Low
Test Clock
TCK
Input
Test Mode Select
TMS
Input
High
Test Data Input
TDI
Input
High
Test Data Output
TDO
Output
High
Yes
Three-Stated
Test Reset
TRST
Input
Low
Thermal Resistor Connections
THERM1,
THERM0
——
Power Supply
VCC
Input
Ground
GND
Input
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