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| 型號(hào)： | MC68EC060RC50 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 88/128頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 50MHZ 206-PGA |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 系列： | M680x0 |
| 處理器類(lèi)型： | M680x0 32-位 |
| 速度： | 50MHz |
| 電壓： | 3.3V |
| 安裝類(lèi)型： | 通孔 |
| 封裝/外殼： | 206-BEPGA |
| 供應(yīng)商設(shè)備封裝： | 206-PGA（47.25x47.25） |
| 包裝： | 托盤(pán) |
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Signal Description
2-16
M68060 USER’S MANUAL
MOTOROLA
state on the rising edge of CLK regardless of the state of the CLKEN) only on those rising
edges of CLK which are spanned by the assertion of CLKEN.
CLKEN may be used to allow the external bus to run at 1/2 or 1/4 the speed of the MC68060
processor clock which controls all internal operations. The MC68060 bus interface controller
will not detect those rising edges of CLK which are spanned with the negation of CLKEN.
To operate the external bus at 1/2 or 1/4 the speed of CLK, CLKEN must be asserted and
stable during the rising edges of CLK which coincide with the system clock running at 1/2 or
1/4 the frequency of the MC68060 processor clock. CLKEN must be negated and stable dur-
ing all other rising CLK edges.
For full speed operation of the MC68060 processor, CLKEN must be continuously asserted.
Refer to Section 7 Bus Operation for more information on the MC68060 bus interface and
controller. Refer to Section 12 Electrical and Thermal Characteristics for the timing spec-
ifications of CLK and CLKEN.
2.11 TEST SIGNALS
The MC68060 includes dedicated user-accessible test logic that is fully compatible with the
IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems asso-
ciated with testing high-density circuit boards have led to the development of this standard
under the IEEE Test Technology Committee and Joint Test Action Group (JTAG) sponsor-
ship. The MC68060 implementation supports circuit board test strategies based on this
standard. However, the JTAG interface is not intended to provide an in-circuit test to verify
MC68060 operations; therefore, it is impossible to test MC68060 operations using this inter-
face. Section 9 IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes describes the
MC68060 implementation of IEEE 1149.1 and is intended to be used with the supporting
IEEE document.
2.11.1 JTAG Enable (JTAG)
This input signal is used to select between 1149.1 operation and debug emulation mode.
The 1149.1 test access port (TAP) pins are remapped to emulation mode functions when
this pin is negated. For normal 1149.1 operation, JTAG should be grounded.
2.11.2 Test Clock (TCK)
This input signal is used as a dedicated clock for the test logic. Since clocking of the test
logic is independent of the normal operation of the MC68060, several other components on
a board can share a common test clock with the processor even though each component
may operate from a different system clock. The design of the test logic allows the test clock
to run at low frequencies, or to be gated off entirely as required for test purposes. TCK
should be grounded if it is not used and emulation mode is not to be used.
2.11.3 Test Mode Select (TMS)
This input signal is decoded by the TAP controller and distinguishes the principal operations
of the test support circuitry. TMS should be tied to VCC if it is not used and emulation mode
is not to be used.
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