- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4100 > MC68EC060RC50 (Freescale Semiconductor)IC MPU 32BIT 50MHZ 206-PGA PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68EC060RC50 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 14/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 50MHZ 206-PGA |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 50MHz |
| 電壓： | 3.3V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 206-BEPGA |
| 供應(yīng)商設(shè)備封裝： | 206-PGA（47.25x47.25） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
Caches
MOTOROLA
M68060 USER’S MANUAL
5-11
cache if the corresponding data in memory is modified. Invalidating instruction cache lines
before writing to the corresponding memory lines can prevent this coherency problem, but
only if the data cache line is in writethrough or cache-inhibited mode. A cache coherency
problem could arise if the data cache line is configured as copyback.
To fully support self-modifying code in any situation, it is imperative that a CPUSHA instruc-
tion specifying both caches be executed before the execution of the first self-modified
instruction. The CPUSHA instruction has the effect of ensuring that there is no stale data in
memory, the pipeline is flushed, and instruction prefetches are repeated and taken from
external memory.
5.7 MEMORY ACCESSES FOR CACHE MAINTENANCE
The cache controller in each memory unit performs all maintenance activities that supply
data from the cache to the instruction and operand pipeline units. The activities include
requesting accesses to the bus interface unit for reading new cache lines and writing dirty
cache lines to memory. The following paragraphs describe the memory accesses resulting
from cache fill operations (by both caches) and push operations (by the data cache). Refer
to Section 7 Bus Operation for detailed information about the bus cycles required.
5.7.1 Cache Filling
When a new cache line is required, the cache controller requests a line read from the bus
controller. The bus controller requests a burst read transfer by indicating a line access with
the size signals (SIZ1, SIZ0) and indicates which line in the set is being loaded with the
transfer line number signals (TLN1, TLN0). TLN1 and TLN0 are undefined for the instruction
cache. These pins indicate the appropriate line numbers for cache transfers. Table 5-1 lists
the definition of the TLNx encoding.
The responding device sequentially supplies four long words of data and can assert the
transfer cache inhibit signal (TCI) if the line is not cachable. If the responding device does
not support the burst mode, it should assert the TBI signal for the first long word of the line
access. The bus controller responds by terminating the line access and completes the
remainder of the line read as three, sequential, long-word reads.
Bus controller line accesses implicitly request burst mode operations from external memory.
To operate in the burst mode, the device or external hardware must be able to increment
the low-order address bits as described in Section 7 Bus Operation. The device indicates
its ability to support the burst access by acknowledging the initial long-word transfer with
transfer acknowledge (TA) asserted and TBI negated. This procedure causes the processor
to continue to drive the address and bus control signals and to latch a new data value for
the cache line at the completion of each subsequent cycle (as defined by TA) for a total of
Table 5-1. TLNx Encoding
TLN1
TLN0
Line
0
Zero
0
1
One
1
0
Two
1
Three
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT71V65803S133BGG8 | IC SRAM 9MBIT 133MHZ 119BGA |
| MPC8270ZUUPEA | IC MPU POWERQUICC II 480-TBGA |
| IDT71V65803S133BG8 | IC SRAM 9MBIT 133MHZ 119BGA |
| MPC860PCZQ66D4 | IC MPU PWRQUICC 66MHZ 357-PBGA |
| IDT71V65803S100BGG8 | IC SRAM 9MBIT 100MHZ 119BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68EC060RC66 | 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68EC060RC75 | 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68EC060ZU50 | 功能描述:IC MPU 68K 50MHZ 304-TBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M680x0 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| MC68EC060ZU66 | 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68EC060ZU75 | 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。