參數(shù)資料
型號： MC68EC060RC50
廠商： Freescale Semiconductor
文件頁數(shù)： 13/128頁
文件大小： 0K
描述： IC MPU 32BIT 50MHZ 206-PGA
標(biāo)準(zhǔn)包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 50MHz
電壓： 3.3V
安裝類型： 通孔
封裝/外殼： 206-BEPGA
供應(yīng)商設(shè)備封裝： 206-PGA（47.25x47.25）
包裝： 托盤
Table of Contents
MOTOROLA
M68060 USER’S MANUAL
xiii
6.1.3.4
Accrued Exception Byte ........................................................................... 6-6
6.1.4
Floating-Point Instruction Address Register (FPIAR) ................................. 6-7
6.2
Floating-Point Data Formats and Data Types............................................... 6-7
6.3
Computational Accuracy ............................................................................. 6-11
6.3.1
Intermediate Result................................................................................... 6-12
6.3.2
Rounding the Result ................................................................................. 6-13
6.4
Postprocessing Operation........................................................................... 6-15
6.4.1
Underflow, Round, and Overflow .............................................................. 6-15
6.4.2
Conditional Testing ................................................................................... 6-16
6.5
Floating-Point Exceptions ........................................................................... 6-19
6.5.1
Unimplemented Floating-Point Instructions .............................................. 6-19
6.5.2
Unsupported Floating-Point Data Types................................................... 6-21
6.5.3
Unimplemented Effective Address Exception ........................................... 6-22
6.6
Floating-Point Arithmetic Exceptions .......................................................... 6-22
6.6.1
Branch/Set on Unordered (BSUN)............................................................ 6-24
6.6.1.1
Trap Disabled Results (FPCR BSUN Bit Cleared) ................................. 6-24
6.6.1.2
Trap Enabled Results (FPCR BSUN Bit Set) ......................................... 6-24
6.6.2
Signaling Not-a-Number (SNAN) .............................................................. 6-25
6.6.2.1
Trap Disabled Results (FPCR SNAN Bit Cleared) ................................. 6-25
6.6.2.2
Trap Enabled Results (FPCR SNAN Bit Set) ......................................... 6-26
6.6.3
Operand Error ........................................................................................... 6-26
6.6.3.1
Trap Disabled Results (FPCR OPERR Bit Cleared)............................... 6-27
6.6.3.2
Trap Enabled Results (FPCR OPERR Bit Set)....................................... 6-27
6.6.4
Overflow.................................................................................................... 6-28
6.6.4.1
Trap Disabled Results (FPCR OVFL Bit Cleared) .................................. 6-29
6.6.4.2
Trap Enabled Results (FPCR OVFL Bit Set) .......................................... 6-29
6.6.5
Underflow.................................................................................................. 6-30
6.6.5.1
Trap Disabled Results (FPCR UNFL Bit Cleared) .................................. 6-31
6.6.5.2
Trap Enabled Results (FPCR UNFL Bit Set) .......................................... 6-31
6.6.6
Divide-by-Zero .......................................................................................... 6-32
6.6.6.1
Trap Disabled Results (FPCR DZ Bit Cleared)....................................... 6-33
6.6.6.2
Trap Enabled Results (FPCR DZ Bit Set)............................................... 6-33
6.6.7
Inexact Result ........................................................................................... 6-33
6.6.7.1
Trap Disabled Results (FPCR INEX1 Bit and INEX2 Bit Cleared........... 6-34
6.6.7.2
Trap Enabled Results (Either FPCR INEX1 Bit or INEX2 Bit Set).......... 6-34
6.7
Floating-Point State Frames ....................................................................... 6-35
Section 7
Bus Operation
7.1
Bus Characteristics ....................................................................................... 7-1
7.2
Full-, Half-, and Quarter-Speed Bus Operation and BCLK ........................... 7-3
7.3
Acknowledge Termination Ignore State Capability ....................................... 7-4
7.4
Bus Control Register..................................................................................... 7-4
7.5
Data Transfer Mechanism............................................................................. 7-5
7.6
Misaligned Operands .................................................................................... 7-9
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