參數(shù)資料
型號: MC68EC060RC50
廠商: Freescale Semiconductor
文件頁數(shù): 102/128頁
文件大?。?/td> 0K
描述: IC MPU 32BIT 50MHZ 206-PGA
標(biāo)準(zhǔn)包裝: 10
系列: M680x0
處理器類型: M680x0 32-位
速度: 50MHz
電壓: 3.3V
安裝類型: 通孔
封裝/外殼: 206-BEPGA
供應(yīng)商設(shè)備封裝: 206-PGA(47.25x47.25)
包裝: 托盤
Memory Management Unit
4-6
M68060 USER’S MANUAL
MOTOROLA
4.1.3 Transparent Translation Registers
The data transparent translation registers (DTTR0 and DTTR1) and instruction transparent
translation registers (ITTR0 and ITTR1) are 32-bit registers that define blocks of logical
address space that are untranslated by the MMU (the logical address is the physical
address). The TTRs operate independently of the E-bit in the TCR and the state of the MDIS
signal. Data transfers to and from these registers are long-word transfers. The TTR fields
are defined following Figure 4-5, which illustrates TTR format. Bits 12–10, 7, 4, 3, 1, and 0
always read as zero.
Bits 31–24—Logical Address Base
This 8-bit field is compared with address bits A31–A24. Addresses that match in this com-
parison (and are otherwise eligible) are transparently translated.
Bits 23–16—Logical Address Mask
Since this 8-bit field contains a mask for the Logical Address Mask field, setting a bit in
this field causes the corresponding bit in the Logical Address Base field to be ignored.
Blocks of memory larger than 16 Mbytes can be transparently translated by setting some
of the logical address mask bits to ones. The low-order bits of this field can be set to define
contiguous blocks larger than 16 Mbytes. The mask can be used to define multiple non-
contiguous blocks of addresses.
E—Enable
This bit enables or disables transparent translation of the block defined by this register:
0 = Transparent translation disabled
1 = Transparent translation enabled
S—Supervisor Mode
This field specifies the way FC2 is used in matching an address:
00 = Match only if FC2 = 0 (user mode access)
01 = Match only if FC2 = 1 (supervisor mode access)
1X = Ignore FC2 when matching
U0, U1—User Page Attributes
The user defines these bits, and the MC68060 does not interpret them. U0 and U1 are
echoed to the UPA0 and UPA1 signals, respectively, if an external bus transfer results
31
24
23
16
15
14
13
12
11
10
9876543210
LOGICAL ADDRESS BASE
LOGICAL ADDRESS MASK
E
S-FIELD
0
U1 U0
0
CM
0
W
0
Figure 4-5. Transparent Translation Register Format
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