參數(shù)資料
型號： MC68EC060RC50
廠商： Freescale Semiconductor
文件頁數(shù)： 62/128頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 50MHZ 206-PGA
標(biāo)準(zhǔn)包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 50MHz
電壓： 3.3V
安裝類型： 通孔
封裝/外殼： 206-BEPGA
供應(yīng)商設(shè)備封裝： 206-PGA（47.25x47.25）
包裝： 托盤
Introduction
MOTOROLA
M68060 USER’S MANUAL
1-15
An instruction’s addressing mode can specify the value of an operand, a register containing
the operand, or how to derive the effective address of an operand in memory. Each address-
ing mode has an assembler syntax. Some instructions imply the addressing mode for an
operand. These instructions include the appropriate fields for operands that use only one
addressing mode. Table 1-2 lists a summary of the effective addressing modes for the
MC68060. Refer to M68000PM/AD,
M68000 Family Programmer’s Reference Manual, for
details on instruction format and addressing modes.
1.9 INSTRUCTION SET OVERVIEW
The instruction set is tailored to support high-level languages and is optimized for those
instructions most commonly executed. The floating-point instructions for the MC68060 are
a commonly used subset of the MC68881/MC68882 instruction set with new arithmetic
instructions to explicitly select single- or double-precision rounding. The remaining unimple-
mented instructions are less frequently used and are efficiently emulated in the
MC68060FPSP, maintaining compatibility with the MC68881/MC68882 floating-point copro-
cessors. The MC68060 instruction set includes MOVE16 which allows high-speed transfers
of 16-byte blocks between external devices such as memory to memory or coprocessor to
memory. Table 1-3 provides an alphabetized listing of the MC68060 instruction set’s
opcode, operation, and syntax. Refer to Table 1-4 for notations used in Table 1-3. The left
operand in the syntax is always the source operand, and the right operand is the destination
operand. Refer to M68000PM/AD,
M68000 Family Programmer’s Reference Manual, for
details on instructions used by the MC68060.
Table 1-2. Effective Addressing Modes
Addressing Modes
Syntax
Register Direct
Data
Address
Dn
An
Register Indirect
Address
Address with Postincrement
Address with Predecrement
Address with Displacement
(An)
(An)+
–(An)
(d16,An)
Address Register Indirect with Index
8-Bit Displacement
Base Displacement
(d8,An,Xn)
(bd,An,Xn)
Memory Indirect
Postindexed
Preindexed
([bd,An],Xn,od)
([bd,An,Xn],od)
Program Counter Indirect
with Displacement
(d16,PC)
Program Counter Indirect with Index
8-Bit Displacement
Base Displacement
(d8,PC,Xn)
(bd,PC,Xn)
Program Counter Memory Indirect
Postindexed
Preindexed
([bd,PC],Xn,od)
([bd,PC,Xn],od)
Absolute Data Addressing
Short
Long
(xxx).W
(xxx).L
Immediate
#<xxx>
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