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| 型號： | MC68EC060RC50 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 84/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 50MHZ 206-PGA |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 50MHz |
| 電壓： | 3.3V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 206-BEPGA |
| 供應(yīng)商設(shè)備封裝： | 206-PGA（47.25x47.25） |
| 包裝： | 托盤 |
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Signal Description
MOTOROLA
M68060 USER’S MANUAL
2-13
2.8.2 MMU Disable (MDIS)
When asserted, this input signal dynamically disables the MC68060 internal operand data
and instruction MMUs on the next internal access boundary. While MDIS is asserted, all
accesses bypass the MMU ATCs, and thus translate transparently. The execution of one of
the MMU flush instructions (PFLUSHA, PFLUSHAN, PFLUSH, PFLUSHN) may cause the
deletion of the MMU entries, even if the MMU has been disabled by this signal. The MMUs
are enabled on the next boundary after MDIS is negated. Refer to Section 4 Memory Man-
agement Unit for a description of address translation.
2.8.3 Reset In (RSTI)
The assertion of this input signal causes the MC68060 to enter reset exception processing.
The RSTI signal is an asynchronous input that is internally synchronized to the next rising
clock-enabled clock (CLK) edge. All three-state signals will eventually be set to the high-
impedance state when RSTI is recognized. The assertion of RSTI does not affect the test
pins. Refer to Section 7 Bus Operation for a description of reset operation and to Section
8 Exception Processing for information about the reset exception.
2.8.4 Reset Out (RSTO)
The MC68060 asserts this output during execution of the RESET instruction to initialize
external devices. All bus cycles by the MC68060 are suspended prior to the assertion of
RSTO, but bus arbitration and snooping still function. Refer to Section 7 Bus Operation for
a description of reset out bus operation.
2.9 INTERRUPT CONTROL SIGNALS
The following signals control the interrupt functions.
2.9.1 Interrupt Priority Level (IPL2–IPL0)
These input signals provide an indication of an interrupt condition with the interrupt level
from a peripheral or external prioritizing circuitry encoded. IPL2 is the most significant bit of
the level number. For example, since the IPLx signals are active low, IPL2–IPL0 = 101 cor-
responds to an interrupt request at interrupt priority level 2. IPL2–IPL0 = 000 (level 7) is the
highest priority interrupt and cannot be internally masked. IPL2–IPL0 = 111 (level 0) indi-
cates no interrupt is requested. The IPLx signals are asynchronous inputs that are internally
synchronized to rising clock (CLK) edges.
During a processor reset, the levels on the IPLx lines are registered and used to configure
the various operating modes for the MC68060 bus. Refer to Section 7 Bus Operation for
more information on bus operating modes and Section 8 Exception Processing for infor-
mation on interrupts.
2.9.2 Interrupt Pending Status (IPEND)
This output signal indicates that an interrupt request has been recognized internally by the
processor and exceeds the current interrupt priority mask in the status register (SR). Exter-
nal devices (other bus masters) can use IPEND to predict processor operation on the next
instruction boundaries. IPEND is not intended for use as an interrupt acknowledge to exter-
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