參數(shù)資料
型號： MC68EC060RC50
廠商： Freescale Semiconductor
文件頁數(shù)： 24/128頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 50MHZ 206-PGA
標(biāo)準(zhǔn)包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 50MHz
電壓： 3.3V
安裝類型： 通孔
封裝/外殼： 206-BEPGA
供應(yīng)商設(shè)備封裝： 206-PGA（47.25x47.25）
包裝： 托盤
Table of Contents
xiv
M68060 USER’S MANUAL
MOTOROLA
7.7
Processor Data Transfers........................................................................... 7-12
7.7.1
Byte, Word, and Long-Word Read Transfer Cycles ................................. 7-12
7.7.2
Line Read Transfer ................................................................................... 7-15
7.7.3
Byte, Word, and Long-Word Write Cycles ................................................ 7-20
7.7.4
Line Write Cycles..................................................................................... 7-25
7.7.5
Locked Read-Modify-Write Cycles .......................................................... 7-28
7.7.6
Emulating CAS2 and CAS Misaligned...................................................... 7-31
7.7.7
Using CLA to Increment A3 and A2.......................................................... 7-32
7.8
Acknowledge Cycles................................................................................... 7-32
7.8.1
Interrupt Acknowledge Cycles ................................................................. 7-32
7.8.1.1
Interrupt Acknowledge Cycle (Terminated Normally) ............................. 7-35
7.8.1.2
Autovector Interrupt Acknowledge Cycle ............................................... 7-35
7.8.1.3
Spurious Interrupt Acknowledge Cycle .................................................. 7-35
7.8.2
Breakpoint Acknowledge Cycle ................................................................ 7-36
7.8.2.1
LPSTOP Broadcast Cycle ...................................................................... 7-38
7.9
Bus Exception Control Cycles .................................................................... 7-46
7.9.1
Bus Errors................................................................................................. 7-46
7.9.2
Retry Operation ........................................................................................ 7-48
7.9.3
Double Bus Fault ...................................................................................... 7-51
7.10
Bus Synchronization ................................................................................... 7-52
7.11
Bus Arbitration ............................................................................................ 7-52
7.11.1
MC68040-Arbitration Protocol (BB Protocol) ............................................ 7-53
7.11.2
MC68060-Arbitration Protocol (BTT Protocol) .......................................... 7-58
7.11.3
External Arbiter Considerations ................................................................ 7-65
7.12
Bus Snooping Operation............................................................................ 7-68
7.13
Reset Operation......................................................................................... 7-71
7.14
Special Modes of Operation ....................................................................... 7-74
7.14.1
Acknowledge Termination Ignore State Capability ................................... 7-74
7.14.2
Acknowledge Termination Protocol .......................................................... 7-76
7.14.3
Extra Data Write Hold Time Mode ............................................................ 7-76
Section 8
Exception Processing
8.1
Exception Processing Overview ................................................................... 8-1
8.2
Integer Unit Exceptions................................................................................. 8-4
8.2.1
Access Error Exception .............................................................................. 8-5
8.2.2
Address Error Exception............................................................................. 8-7
8.2.3
Instruction Trap Exception .......................................................................... 8-7
8.2.4
Illegal Instruction and Unimplemented Instruction Exceptions ................... 8-8
8.2.5
Privilege Violation Exception .................................................................... 8-10
8.2.6
Trace Exception........................................................................................ 8-10
8.2.7
Format Error Exception ............................................................................ 8-11
8.2.8
Breakpoint Instruction Exception .............................................................. 8-11
8.2.9
Interrupt Exception ................................................................................... 8-12
8.2.10
Reset Exception ....................................................................................... 8-14
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