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| 型號： | MC68EC060RC50 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 23/128頁 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 50MHZ 206-PGA |
| 標準包裝： | 10 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 50MHz |
| 電壓： | 3.3V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 206-BEPGA |
| 供應商設備封裝： | 206-PGA（47.25x47.25） |
| 包裝： | 托盤 |
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MOTOROLA
M68060 USER’S MANUAL
6-1
SECTION 6
FLOATING-POINT UNIT
NOTE
This section does not apply to the MC68LC060 or MC68EC060.
Refer
to
Appendix
A
MC68LC060
and
Appendix
B
MC68EC060 for details.
Floating-point math refers to numeric calculations with a variable decimal point location. It
is distinguished from integer math, which deals only with whole numbers and fixed decimal
point locations. Historically, general-purpose microprocessors have had to depend on add-
on coprocessors and accelerators such as the MC68881/MC68882 for fast floating-point
capabilities. The MC68060 features a built-in floating-point unit (FPU). Consolidating this
important function on chip speeds up the overall processing and eliminates interfacing over-
head required for external accelerators. The MC68060 FPU operates in parallel with the
integer unit. The FPU does the numeric calculation while the integer unit performs other
tasks. When used with Motorola-supplied emulation software, the M68060 software pack-
age (M68060SP), the MC68060 FPU is fully compliant with the
ANSI/IEEE 754–1985 Stan-
dard for Binary Floating-Point Arithmetic.
The on-chip FPU (shown in Figure 6-1) consists of four functional units: FPADD, FPMUL,
FPDIV, and FPMISC. These functional units exist in parallel with the integer unit. The
decode of floating-point operations is done in the same pipeline stage as integer instruc-
tions, and operands are fetched by the same logic which feeds the integer unit. The floating-
point functional units are located in the primary pipeline of the integer unit. Only one floating-
point functional unit at a time can be active. The FPU allows no concurrency between float-
ing-point instructions to achieve a streamlined floating-point exception model.
The FPADD unit performs floating-point addition and subtraction, compare, absolute value,
negate, floating-point to integer and integer to floating-point conversions, and move-in and
move-out of floating-point data when the precision and destination are not single, double, or
extended precision. Results produced in this unit are rounded to the desired precision and
rounding mode. The FPMUL unit performs floating-point multiply and rounding to desired
precision and rounding mode. The FPDIV unit performs floating-point divide, square root,
and move-in and move-out of floating-point data when the precision and destination are sin-
gle, double, or extended precision. Results produced in the FDIV unit are rounded to the
desired precision and rounding mode. The FPMISC unit handles the remaining functions
within the FPU. This includes logic for FSAVE and FRESTORE, logic for FMOVEM, and
exception logic. The floating-point control register (FPCR) and floating-point status register
(FPSR) reside within this block. All of these functional units access the floating-point register
file, which contains the program-visible register set.
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