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| 型號： | MC68EC060RC50 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 80/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 50MHZ 206-PGA |
| 標準包裝： | 10 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 50MHz |
| 電壓： | 3.3V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 206-BEPGA |
| 供應商設備封裝： | 206-PGA（47.25x47.25） |
| 包裝： | 托盤 |
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Signal Description
MOTOROLA
M68060 USER’S MANUAL
2-9
2.4.1 Transfer Start (TS)
The processor asserts this three-state bidirectional signal for one clock-enabled clock period
to indicate the start of each bus cycle. During alternate bus master accesses, the processor
monitors TS and SNOOP to detect the start of each bus cycle which is to be snooped. TS
is placed in a high-impedance state when the MC68060 is not the bus master. To properly
maintain internal state information, all masters on the bus must have their TS signals tied
together.
2.4.2 Transfer in Progress (TIP)
This three-state output is asserted to indicate that a bus cycle is in progress and is negated
during idle bus cycles if the bus is still granted to the processor. TIP remains asserted during
the time between back-to-back bus cycles.
If the MC68060 relinquishes the bus while TIP is asserted, TIP will be negated for one clock
period after completion of the final transfer and then goes to a high-impedance state one
clock period after the address is idled. Note that this one clock period in which TIP is driven
negated refers to an MC68060 processor clock period, not a full clock-enabled clock period.
If TIP was already negated in the clock period in which the MC68060 relinquishes the bus,
it will be placed in a high-impedance state in the same clock period that the address bus
becomes idle.
2.4.3 Starting Termination Acknowledge Signal Sampling (SAS)
This three-state output is asserted for one clock-enabled clock period to indicate that the
MC68060 will begin sampling TA, TEA, TRA, TBI, TCI, AVEC, and spurious interrupt indi-
cation on the next rising edge of the clock-enabled clock. SAS is negated at all other times
while the MC68060 is the bus master. When the MC68060 relinquishes the bus, SAS is
driven negated for one clock-enabled clock period and then three-stated one clock-enabled
clock period after the address bus is idled. When the MC68060 newly gains bus ownership
and immediately starts a bus cycle with the assertion of TS, SAS remains three-stated until
the clock-enabled clock period after TS is asserted.
2.5 SLAVE TRANSFER CONTROL SIGNALS
The following signals provide control functions for bus transfers when the MC68060 is not
the bus master. Refer to Section 7 Bus Operation for detailed information about the rela-
tionship of the bus cycle control signals to bus operation.
2.5.1 Transfer Acknowledge (TA)
This input indicates the completion of a requested data transfer operation. During transfers
by the MC68060, TA is an input signal from the referenced slave device indicating comple-
tion of the transfer. For the MC68060 to accept the transfer as successful with a transfer
acknowledge, TRA and TEA must be negated when TA is asserted.
2.5.2 Transfer Retry Acknowledge (TRA)
For native-MC68060-style (non-MC68040-style) acknowledge termination, this input signal
may be asserted by the current slave on the first transfer of a bus cycle to indicate the need
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