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| 型號： | MC68EC060RC50 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 82/128頁 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 50MHZ 206-PGA |
| 標準包裝： | 10 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 50MHz |
| 電壓： | 3.3V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 206-BEPGA |
| 供應(yīng)商設(shè)備封裝： | 206-PGA（47.25x47.25） |
| 包裝： | 托盤 |
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Signal Description
MOTOROLA
M68060 USER’S MANUAL
2-11
2.7 ARBITRATION SIGNALS
The following control signals support bus mastership control by an external arbiter over the
MC68060. Refer to Section 7 Bus Operation for detailed information about the relationship
of the arbitration signals to bus operation.
2.7.1 Bus Request (BR)
This output signal indicates to an external arbiter that the processor needs to become bus
master for one or more bus cycles. BR is negated when the MC68060 begins an access to
the external bus with no other internal accesses pending, and BR remains negated until
another internal request occurs. The assertion and negation of BR are independent of bus
activity and there are some situations in which the MC68060 asserts BR and then negates
it without having run a bus cycle; this is a disregard request condition. Refer to Section 7
Bus Operation for details about this state.
2.7.2 Bus Grant (BG)
This input signal from an external arbiter indicates that the bus is available to the MC68060
as soon as the current bus cycle completes. The MC68060 assumes bus ownership when
BG is asserted and BB is negated, when BG is asserted and a TS-BTT pair (TS asserted,
followed by BTT asserted) has occurred in the past without another assertion of TS, or when
BG and BTT are asserted and TS is negated. The MC68060 indicates its ownership of the
bus by asserting BB. When the external arbiter negates BG, the MC68060 relinquishes the
bus as soon as the current bus cycle is complete unless a locked sequence of bus cycles is
in progress with BGR negated. In this case, the MC68060 will complete the entire sequence
of locked bus cycles and then indicate that it is relinquishing the bus by asserting BTT and
negating BB.
2.7.3 Bus Grant Relinquish Control (BGR)
This input signal is a qualifier for BG and indicates to the MC68060 the degree of necessity
for relinquishing bus ownership when BG is negated by an external arbiter. BGR controls
MC68060 behavior when BG is negated during sequences of locked bus cycles (LOCK
asserted). When the external arbiter negates BG during a series of locked bus cycles, the
assertion of BGR will cause the MC68060 to relinquish the bus on the last transfer of the
current bus cycle, even though the MC68060 had intended the series to be locked. If BGR
remains negated when BG is negated during locked transfers, then the MC68060 will not
relinquish the bus until the series of locked bus cycles is complete.
2.7.4 Bus Tenure Termination (BTT)
This three-state bidirectional signal is asserted for one clock-enabled clock period and
negated for one clock-enabled clock period to indicate that the MC68060 has relinquished
its bus tenure following the negation of BG by an external arbiter. At all other times, BTT is
in a high-impedance state. When an alternate master is controlling the bus, the MC68060
samples BTT as an input to maintain internal state information and to monitor when the
MC68060 may become the bus master. To properly maintain this internal state information,
all masters on the bus must have their TS signals tied together and their BTT signals tied
together so the MC68060 can keep track of TS-BTT pairs.
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