- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4100 > MC68EC060RC50 (Freescale Semiconductor)IC MPU 32BIT 50MHZ 206-PGA PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68EC060RC50 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 82/128頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 50MHZ 206-PGA |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 50MHz |
| 電壓： | 3.3V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 206-BEPGA |
| 供應(yīng)商設(shè)備封裝： | 206-PGA（47.25x47.25） |
| 包裝： | 托盤 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)當(dāng)前第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
Signal Description
MOTOROLA
M68060 USER’S MANUAL
2-11
2.7 ARBITRATION SIGNALS
The following control signals support bus mastership control by an external arbiter over the
MC68060. Refer to Section 7 Bus Operation for detailed information about the relationship
of the arbitration signals to bus operation.
2.7.1 Bus Request (BR)
This output signal indicates to an external arbiter that the processor needs to become bus
master for one or more bus cycles. BR is negated when the MC68060 begins an access to
the external bus with no other internal accesses pending, and BR remains negated until
another internal request occurs. The assertion and negation of BR are independent of bus
activity and there are some situations in which the MC68060 asserts BR and then negates
it without having run a bus cycle; this is a disregard request condition. Refer to Section 7
Bus Operation for details about this state.
2.7.2 Bus Grant (BG)
This input signal from an external arbiter indicates that the bus is available to the MC68060
as soon as the current bus cycle completes. The MC68060 assumes bus ownership when
BG is asserted and BB is negated, when BG is asserted and a TS-BTT pair (TS asserted,
followed by BTT asserted) has occurred in the past without another assertion of TS, or when
BG and BTT are asserted and TS is negated. The MC68060 indicates its ownership of the
bus by asserting BB. When the external arbiter negates BG, the MC68060 relinquishes the
bus as soon as the current bus cycle is complete unless a locked sequence of bus cycles is
in progress with BGR negated. In this case, the MC68060 will complete the entire sequence
of locked bus cycles and then indicate that it is relinquishing the bus by asserting BTT and
negating BB.
2.7.3 Bus Grant Relinquish Control (BGR)
This input signal is a qualifier for BG and indicates to the MC68060 the degree of necessity
for relinquishing bus ownership when BG is negated by an external arbiter. BGR controls
MC68060 behavior when BG is negated during sequences of locked bus cycles (LOCK
asserted). When the external arbiter negates BG during a series of locked bus cycles, the
assertion of BGR will cause the MC68060 to relinquish the bus on the last transfer of the
current bus cycle, even though the MC68060 had intended the series to be locked. If BGR
remains negated when BG is negated during locked transfers, then the MC68060 will not
relinquish the bus until the series of locked bus cycles is complete.
2.7.4 Bus Tenure Termination (BTT)
This three-state bidirectional signal is asserted for one clock-enabled clock period and
negated for one clock-enabled clock period to indicate that the MC68060 has relinquished
its bus tenure following the negation of BG by an external arbiter. At all other times, BTT is
in a high-impedance state. When an alternate master is controlling the bus, the MC68060
samples BTT as an input to maintain internal state information and to monitor when the
MC68060 may become the bus master. To properly maintain this internal state information,
all masters on the bus must have their TS signals tied together and their BTT signals tied
together so the MC68060 can keep track of TS-BTT pairs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT71V65803S133BGG8 | IC SRAM 9MBIT 133MHZ 119BGA |
| MPC8270ZUUPEA | IC MPU POWERQUICC II 480-TBGA |
| IDT71V65803S133BG8 | IC SRAM 9MBIT 133MHZ 119BGA |
| MPC860PCZQ66D4 | IC MPU PWRQUICC 66MHZ 357-PBGA |
| IDT71V65803S100BGG8 | IC SRAM 9MBIT 100MHZ 119BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68EC060RC66 | 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68EC060RC75 | 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68EC060ZU50 | 功能描述:IC MPU 68K 50MHZ 304-TBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M680x0 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| MC68EC060ZU66 | 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68EC060ZU75 | 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。