參數(shù)資料
型號(hào)： MC68EC060RC50
廠商： Freescale Semiconductor
文件頁數(shù)： 38/128頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 50MHZ 206-PGA
標(biāo)準(zhǔn)包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 50MHz
電壓： 3.3V
安裝類型： 通孔
封裝/外殼： 206-BEPGA
供應(yīng)商設(shè)備封裝： 206-PGA（47.25x47.25）
包裝： 托盤
MOTOROLA
M68060 USER’S MANUAL
xix
LIST OF ILLUSTRATIONS
1-1
MC68060 Block Diagram ................................................................................... 1-6
1-2
Programming Model ......................................................................................... 1-12
2-1
Functional Signal Groups ................................................................................... 2-3
3-1
MC68060 Integer Unit Pipeline .......................................................................... 3-1
3-2
Integer Unit User Programming Model............................................................... 3-2
3-3
Integer Unit Supervisor Programming Model ..................................................... 3-3
3-4
Status Register................................................................................................... 3-4
3-5
Processor Configuration Register ...................................................................... 3-5
4-1
Memory Management Unit ................................................................................. 4-2
4-2
Memory Management Programming Model ....................................................... 4-3
4-3
URP and SRP Register Formats........................................................................ 4-3
4-4
Translation Control Register Format .................................................................. 4-4
4-5
Transparent Translation Register Format .......................................................... 4-6
4-6
Translation Table Structure ................................................................................ 4-8
4-7
Logical Address Format ..................................................................................... 4-8
4-8
Detailed Flowchart of Table Search Operation ................................................ 4-10
4-9
Detailed Flowchart of Descriptor Fetch Operation ........................................... 4-11
4-10
Table Descriptor Formats................................................................................. 4-12
4-11
Page Descriptor Formats ................................................................................. 4-12
4-12
Example Translation Table............................................................................... 4-15
4-13
Translation Table Using Indirect Descriptors ................................................... 4-16
4-14
Translation Table Using Shared Tables ........................................................... 4-18
4-15
Translation Table with Nonresident Tables ...................................................... 4-19
4-16
Translation Table Structure for Two Tasks ...................................................... 4-21
4-17
Logical Address Map with Shared Supervisor and User Address Spaces....... 4-22
4-18
Translation Table Using S-Bit and W-Bit To Set Protection ............................. 4-23
4-19
ATC Organization............................................................................................. 4-24
4-20
ATC Entry and Tag Fields ................................................................................ 4-25
4-21
Address Translation Flowchart......................................................................... 4-29
5-1
MC68060 Instruction and Data Caches ............................................................. 5-2
5-2
Instruction Cache Line Format ........................................................................... 5-2
5-3
Data Cache Line Format .................................................................................... 5-2
5-4
Caching Operation ............................................................................................. 5-3
5-5
Cache Control Register ...................................................................................... 5-5
5-6
Instruction Cache Line State Diagram.............................................................. 5-16
5-7
Data Cache Line State Diagrams..................................................................... 5-18
6-1
Floating-Point Unit Block Diagram ..................................................................... 6-2
6-2
Floating-Point User Programming Model ........................................................... 6-3
6-3
Floating-Point Control Register Format.............................................................. 6-4
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MC68EC060RC66 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC68EC060RC75 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC68EC060ZU50 功能描述:IC MPU 68K 50MHZ 304-TBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M680x0 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤
MC68EC060ZU66 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC68EC060ZU75 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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