參數(shù)資料
型號： MC68EC060RC50
廠商： Freescale Semiconductor
文件頁數(shù)： 43/128頁
文件大小： 0K
描述： IC MPU 32BIT 50MHZ 206-PGA
標準包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 50MHz
電壓： 3.3V
安裝類型： 通孔
封裝/外殼： 206-BEPGA
供應(yīng)商設(shè)備封裝： 206-PGA（47.25x47.25）
包裝： 托盤
MOTOROLA
M68060 USER’S MANUAL
xxiii
LIST OF TABLES
1-1
Data Formats.................................................................................................... 1-14
1-2
Effective Addressing Modes............................................................................. 1-15
1-3
Instruction Set Summary .................................................................................. 1-16
1-4
Notational Conventions .................................................................................... 1-21
2-1
Signal Index........................................................................................................ 2-1
2-2
Transfer-Type Encoding..................................................................................... 2-4
2-3
Normal and MOVE16 Access TMx Encoding..................................................... 2-5
2-4
Alternate Access TMx Encoding ........................................................................ 2-5
2-5
SIZx Encoding .................................................................................................... 2-6
2-6
Data Bus Byte Select Signals............................................................................. 2-7
2-7
PSTx Encoding................................................................................................. 2-14
2-8
Signal Summary ............................................................................................... 2-17
4-1
Updating U-Bit and M-Bit for Page Descriptors................................................ 4-20
4-2
SFC and DFC Values....................................................................................... 4-20
5-1
TLNx Encoding................................................................................................. 5-11
5-2
Instruction Cache Line State Transitions.......................................................... 5-15
5-3
Data Cache Line State Transitions................................................................... 5-18
6-1
RND Encoding.................................................................................................... 6-4
6-2
PREC Encoding ................................................................................................. 6-4
6-3
MC68060 FPU Data Formats and Data Types .................................................. 6-7
6-4
Single-Precision Real Format Summary ............................................................ 6-8
6-5
Double-Precision Real Format Summary........................................................... 6-9
6-6
Extended-Precision Real Format Summary ..................................................... 6-10
6-7
Packed Decimal Real Format Summary .......................................................... 6-11
6-8
Floating-Point Condition Code Encoding ......................................................... 6-16
6-9
Floating-Point Conditional Tests ...................................................................... 6-18
6-10
Floating-Point Exception Vectors ..................................................................... 6-19
6-11
Unimplemented Instructions............................................................................. 6-20
6-12
Possible Operand Errors Exceptions ............................................................... 6-27
6-13
Overflow Rounding Mode Values..................................................................... 6-29
6-14
Underflow Rounding Mode Values................................................................... 6-31
6-15
Possible Divide-by-Zero Exceptions................................................................. 6-33
6-16
Rounding Mode Values .................................................................................... 6-34
7-1
Data Bus Requirements for Read and Write Cycles .......................................... 7-7
7-2
Summary of Access Types vs. Bus Signal Encoding......................................... 7-9
7-3
Memory Alignment Influence on Noncachable and
Writethrough Bus Cycles.................................................................................. 7-12
7-4
Interrupt Acknowledge Termination Summary ................................................. 7-34
7-5
Termination Result Summary........................................................................... 7-46
7-6
MC68040-Arbitration Protocol Transition Conditions ....................................... 7-55
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