參數(shù)資料
型號(hào): MC68EC060RC50
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 83/128頁(yè)
文件大?。?/td> 0K
描述: IC MPU 32BIT 50MHZ 206-PGA
標(biāo)準(zhǔn)包裝: 10
系列: M680x0
處理器類型: M680x0 32-位
速度: 50MHz
電壓: 3.3V
安裝類型: 通孔
封裝/外殼: 206-BEPGA
供應(yīng)商設(shè)備封裝: 206-PGA(47.25x47.25)
包裝: 托盤
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)當(dāng)前第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
Signal Description
2-12
M68060 USER’S MANUAL
MOTOROLA
The MC68060 provides the BB signal and protocol to provide compatibility with MC68040-
style buses. Either the BTT signal and protocol or the BB signal and protocol (but not both)
should be used. The unused signal, either BTT or BB, must be pulled up with a pullup resis-
tor and tied to VCC. Use of the BTT signal and protocol yields higher performance at full bus
speed and high operating frequencies. The use of BB and its associated protocol is not rec-
ommended at full bus speeds. The BTT protocol is discussed in detail in Section 7 Bus Op-
eration.
2.7.5 Bus Busy (BB)
This three-state bidirectional signal indicates that the bus is currently owned. BB is moni-
tored as a processor input to determine when an alternate bus master has released control
of the bus. The MC68060 samples bus availability on each clock-enabled clock edge. BG
must be asserted and both TS and BB must be negated (indicating the bus is free) before
the MC68060 asserts BB (with the first assertion of TS) as an output to assume ownership
of the bus. The processor keeps BB asserted until the external arbiter negates BG and the
processor completes the bus cycle in progress. When releasing the bus, the processor
negates BB for one clock period, then places it in a high-impedance state and begins to
sample it as an input. Note that the one clock period in which BB is negated is one MC68060
processor clock period, not a full clock-enabled clock period.
The MC68060 provides the BB signal and protocol to support compatibility with MC68040-
style buses. Either the BTT signal and protocol or the BB signal and protocol (but not both)
should be used. The unused signal, either BTT or BB, must be pulled up through a pullup
resistor and tied to VCC. Use of the BTT signal and protocol yields higher performance at full
bus speed and high operating frequencies. The use of BB and its associated protocol is not
recommended at full bus speeds. The BTT protocol is discussed in detail in Section 7 Bus
Operation.
2.8 PROCESSOR CONTROL SIGNALS
The following signals control the caches and MMUs and support processor and external
device initialization.
2.8.1 Cache Disable (
CDIS)
When asserted, this input signal dynamically disables the on-chip caches on the next inter-
nal cache access boundary. The caches are enabled on the next boundary after CDIS is
negated.
CDIS does not flush the data and instruction caches. Cache entries remain unaltered and
become available after CDIS is negated, unless one of the cache invalidate instructions
(CINVA, CINVP, CINVL) are executed. The execution of one of the cache invalidate instruc-
tions may invalidate entries even if the caches have been disabled with this signal. The
assertion of CDIS does not affect snooping.
Refer to Section 5 Caches for information about the caches.
相關(guān)PDF資料
PDF描述
IDT71V65803S133BGG8 IC SRAM 9MBIT 133MHZ 119BGA
MPC8270ZUUPEA IC MPU POWERQUICC II 480-TBGA
IDT71V65803S133BG8 IC SRAM 9MBIT 133MHZ 119BGA
MPC860PCZQ66D4 IC MPU PWRQUICC 66MHZ 357-PBGA
IDT71V65803S100BGG8 IC SRAM 9MBIT 100MHZ 119BGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68EC060RC66 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC68EC060RC75 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC68EC060ZU50 功能描述:IC MPU 68K 50MHZ 304-TBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M680x0 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA(29x29) 包裝:托盤
MC68EC060ZU66 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC68EC060ZU75 功能描述:微處理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324