參數(shù)資料
型號(hào)： MC68EC060RC50
廠商： Freescale Semiconductor
文件頁數(shù)： 69/128頁
文件大小： 0K
描述： IC MPU 32BIT 50MHZ 206-PGA
標(biāo)準(zhǔn)包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 50MHz
電壓： 3.3V
安裝類型： 通孔
封裝/外殼： 206-BEPGA
供應(yīng)商設(shè)備封裝： 206-PGA（47.25x47.25）
包裝： 托盤
Introduction
MOTOROLA
M68060 USER’S MANUAL
1-21
1.10 NOTATIONAL CONVENTIONS
Table 1-4 lists the notation conventions used throughout this manual.
NOTES:
1.Where d is direction, left or right.
2.Emulation support only, not supported in hardware.
3.Where r is rounding precision, single or double precision.
4.List refers to register.
5.List refers to control registers only.
6.MOVE16 (ax)+,(ay)+ is functionally the same as MOVE16 (ax),(ay)+ when ax = ay. The address register is
only incremented once, and the line is copied over itself rather than to the next line.
7.Not available for the MC68EC060.
8.Emulation support for misaligned operands.
9.Emulation support for FMCVEM with dynamic register list.
Table 1-4. Notational Conventions
Single- And Double-Operand Operations
+
Arithmetic addition or postincrement indicator.
–
Arithmetic subtraction or predecrement indicator.
×
Arithmetic multiplication.
÷
Arithmetic division or conjunction symbol.
~
Invert; operand is logically complemented.
Logical AND
+
Logical OR
⊕
Logical exclusive OR
Source operand is moved to destination operand.
Two operands are exchanged.
<op>
Any double-operand operation.
<operand>tested
Operand is compared to zero and the condition codes are set appropriately.
sign-extended
All bits of the upper portion are made equal to the high-order bit of the lower portion.
Other Operations
TRAP
Equivalent to Format
÷ Offset Word (SSP); SSP – 2 SSP; PC (SSP); SSP – 4 SSP; SR
(SSP); SSP – 2 SSP; (Vector) PC
STOP
Enter the stopped state, waiting for interrupts.
<operand>10
The operand is BCD; operations are performed in decimal.
If <condition>
then <operations>
else <operations>
Test the condition. If true, the operations after “then” are performed. If the condition is false and
the optional “else” clause is present, the operations after “else” are performed. If the condition is
false and else is omitted, the instruction performs no operation. Refer to the Bcc instruction de-
scription as an example.
Register Specification
An
Any Address Register n (example: A3 is address register 3)
Ax, Ay
Source and destination address registers, respectively.
BR
Base Register—An, PC, or suppressed.
Dc
Data register D7–D0, used during compare.
Dh, Dl
Data registers high- or low-order 32 bits of product.
Dn
Any Data Register n (example: D5 is data register 5)
Dr, Dq
Data register’s remainder or quotient of divide.
Du
Data register D7–D0, used during update.
Dx, Dy
Source and destination data registers, respectively.
MRn
Any Memory Register n.
Table 1-3. Instruction Set Summary (Continued)
Opcode
Operation
Syntax
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