參數(shù)資料
型號(hào)： LM98640W-MPR
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, CQFP68
封裝： CERAMIC, QFP-68
文件頁數(shù)： 31/50頁
文件大?。?/td> 1688K
代理商： LM98640W-MPR
Registers
need
to
be
written
with
baseline
values
after
power-up
to
place
part
in
a
valid
state.
Address
(Binary)
Register
Title
(Mnemonic)
Baseline
(Binary)
Register/Bit
Description
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
01
1010
FDAC2
0000
Not
Used
Offset
Bit
8
01
1011
FDAC2
1111
Offset
Value
bits
7:0
01
1100
PGA2
0110
0001
PGA
Gain
Value
01
1101
Reserved
0000
Not
Used
01
1110
Reserved
0000
Not
Used
01
1111
Reserved
0000
Not
Used
Timing
Configuration
10
0000
Clamp
Start
0000
1000
Not
Used
Clamp
Start
Index
10
0001
Clamp
End
0001
1100
Not
Used
Clamp
End
Index
10
0010
Sample
Start
0010
1000
Not
Used
Sample
Start
Index
10
0011
Sample
End
0011
1100
Not
Used
Sample
End
Index
10
0100
Reserved
0011
0100
Reserved
10
0101
INCLK
Range
0000
0010
Not
Used
INCLK
Range
Not
Used
Reserved
10
0110
Reserved
0000
Not
Used
10
0111
Reserved
0000
Not
Used
10
1000
DLL
Configuration
0000
1111
Reserved
DLL
Reset
10
1001
Reserved
0000
Not
Used
10
1010
Reserved
0000
Not
Used
10
1011
Reserved
0000
Not
Used
10
1100
Reserved
0000
Not
Used
10
1101
Reserved
0000
Not
Used
10
1110
Reserved
0000
Not
Used
10
1111
Reserved
0000
Not
Used
Digital
Configuration
Registers
11
0000
Test
Pattern
Start
0000
Start
Upper
Bits
11
0001
Test
Pattern
Start
0000
Start
Lower
Bits
11
0010
Test
Pattern
Width
0000
Width
Upper
Bits
11
0011
Test
Pattern
Width
0000
Width
Lower
Bits
11
0100
Test
Pattern
Control
0000
Pattern
Enable
Pattern
Mode
Pseudo
Random
Enable
Seed
Enable
Pattern
Output
Channel
11
0101
Test
Pattern
Pitch
0000
Test
Pattern
Pitch
11
0110
Test
Pattern
Step
0000
Test
Pattern
Step
Code
37
www.national.com
LM98640QML
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